mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 106

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Package Information and Contact Assignments
5.2.2
Figure 66
106
A NC
B KEY_
C KEY_
D KEY_
E I2C1_
F I2C2_
G I2C3_
H UART
K UART
L UART
M CSPI
N ECS
P SD1_
R SD1_
T SD2_
U SD2_
V SD2_
WSD2_
Y NC
J UART
COL0
COL2
MOSI
ROW
1_TX
1_CT
1_RX
2_TX
_SCL
CMD
PI2_
SCL
SCL
SCL
CLK
CD
D1
D1
D7
D
D
D
1
0
S
K
KEY_C
KEY_C
KEY_R
I2C1_S
I2C2_S
I2C3_S
UART4
UART3
SD1_D
SD1_D
SD2_D
SD2_D
SD2_D
EIM_R
UART1
UART2
1_SCL
PMIC_
STBY_
ECSPI
2_SS0
ECSPI
_TXD
_TXD
_RXD
_RTS
SD2_
OW1
REQ
OL1
OL3
WP
DY
DA
DA
DA
K
2
3
0
5
4
2
shows the 400 MAPBGA 17 x 17 mm ball map.
SSI_R
CSPI_
BOOT
_MOD
BOOT
_MOD
400 MAPBGA 17 x 17 mm Ball Map
SSI_T
SSI_T
UART
UART
ECSP
ECSP
I1_SS
RESE
T_IN_
KEY_
KEY_
4_RX
3_RX
MOSI
I1_MI
SD1_
SD2_
SD2_
PMIC
_ON_
EIM_
EIM_
ROW
ROW
PWM
CRE
REQ
XFS
CLK
OE
SO
XD
XC
D2
D0
E1
E0
D
D
B
3
2
3
2
0
ECSP
ECSP
ECSP
WAIT
PWM
WDO
_SS0
I2_MI
SD1_
SD2_
SD2_
TEST
EIM_
EIM_
EIM_
EIM_
CSPI
CSPI
_MIS
CMD
CKIH VDD2
ECKI
SSI_
SSI_
RXC
I1_M
_MO
CKIL POR_
TXD
I2_S
CLK
EB0
EB1
LBA
OSI
SO
D6
D3
DE
G
O
4
1
L
SSI_R
NVCC
NVCC
NVCC
NVCC
NVCC
NVCC
NVCC
NVCC
BCLK
OWIR
_UAR
VDD3
DA14
DA15
_KEY
_SD1
_SD2
_SRT
EIM_
EIM_
EIM_
EIM_
EPIT
_MIS
_SSI
_SPI
XFS
PAD
VSS VDD_
VSS EXTA
RW
P0
P5
O
C
C
5
E
T
B
i.MX50 Applications Processors for Consumer Products, Rev. 0
_DCD
C_SD
C_RE
VDD1
VDD1
DA12
DA13
DA10
DA11
XTAL USB_O
EIM_
EIM_
EIM_
EIM_
C_EI
GND
EPD
NVC
VDD
VDD
VDD
VDD
VDD
NVC
DCD
CE5
VSS
VSS
SET
GP
GP
GP
GP
GP
CO
P2
P8
M
C
6
L
EIM_DA
EIM_DA
EIM_DA
EIM_DA
PWRCO
VDDGP VDDG
VDDGP VDDG
VDDGP
VDDGP
JTAG_T
EPDC_
NVCC_
VDD_D
GND_K
USB_O
TG_GP
USB_O
TG_RR
EFEXT
ANAIO
TG_ID
RSTB
CDCI
VSS
VSS
VSS
VSS
EIM
EL
M
7
8
9
6
7
Figure 66. 400 MAPBGA 17 x 17 Ball Map
EIM_D
EIM_D
EIM_D
JTAG_
JTAG_
JTAG_
EPDC
EPDC
NVCC
_SDS
_SDC
USB_
OTG_
VBUS
USB_
OTG_
USB_
OTG_
_EIM
MOD
VSS
VSS
VSS
VSS
VSS
VSS NVCC_
TCK
TDI
HR
DN
DP
A5
A2
A3
E3
8
P
P
VDDGP VDDG
VDDGP VDDG
JTAG_T
JTAG_T
NVCC_
USB_O
EPDC_
VDDAL
USB_H
1_RRE
USB_H
TG_VD
USB_H
1_VDD
EIM_D
EIM_D
EIM_C
EIM_C
PWRC
1_VBU
EPDC
VDDA
FEXT
TRL1
JTAG
DA25
VSS
VSS
VSS
A25
MS
DO
A4
A1
S1
S2
S
9
1
CHGR_
EPDC_
EPDC_
EPDC_
SDCE4
EPDC_
NVCC_
VDDAL
NVCC_
USB_H
USB_H
USB_H
DET_B
EIM_D
GDOE
PWRC
1_GPA
GDRL
EPDC
DISP_
TRL0
NAIO
1_DN
1_DP
VCC
VCC
VCC
VSS
LCD
VSS
WR
10
A0
P
P
1
DISP_D
DISP_B
DISP_D
GDCLK
NVCC_
NVCC_
NANDF
USB_O
EPDC_
EPDC_
SDCE2
EPDC_
EPDC_
USB_H
1_VDD
TG_VD
EIM_C
GDSP
EPDC
VDDA
DA33
VCC
VCC
VCC
USY
VSS
VSS
VSS
VSS
D14
A33
S0
11
1
0
EPDC_
SDCE1
EPDC_
SDCE0
EPDC_
EPDC_
SDCLK
EPDC_
NVCC_
NVCC_
NANDF
PWRS
PWRC
DISP_
DISP_
DISP_
DISP_
DISP_
EPDC
TRL2
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
TAT
CS
D6
RD
D2
RS
12
N
C_SD
C_SD
C_D5
C_D1
C_D1
C_D1
DISP
_D13
DISP
DISP
DISP
DISP
EPD
EPD
EPD
EPD
EPD
EPD
VSS
VSS
VSS
VSS NVCC_
VSS
VSS
VSS NVCC_
VSS
VSS
CLK
_D5
_D7
_D3
_D4
OE
13
0
5
2
EPDC_
EPDC_
EPDC_
EPDC_
EPDC_
EPDC_
RESET
EMI_D
SD3_C
VCOM
EMI_D
DISP_
DISP_
DISP_
DISP_
RAM
RAM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D13
D11
D14
D12
D11
D1
D6
D7
LK
14
0
EPDC_
EPDC_
EPDC_
EPDC_
EPDC_
EPDC_
EPDC_
NVCC_
NVCC_
NVCC_
NVCC_
NVCC_
SD3_D
SD3_D
PWRC
VCOM
EMI_D
EMI_D
EMI_D
EMI_D
EMI_D
DISP_
DISP_
DISP_
BDR0
SDLE
TRL3
RAM
RAM
RAM
RAM
RAM
VSS
VSS
VSS
D15
D0
D4
D8
D9
D8
15
1
7
3
NVCC_
NVCC_
NVCC_
NVCC_
NVCC_
NVCC_
NVCC_
NVCC_
EPDC_
EPDC_
EPDC_
EPDC_
EPDC_
EPDC_
SD3_D
SD3_C
SD3_D
EMI_D
EMI_D
EMI_D
EMI_D
EMI_D
EMI_D
EMI_D
EMI_D
DRAM
DISP_
SDOE
SDOE
BDR1
_D26
SD3_
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
D10
MD
WP
D2
D3
D9
16
D
Z
2
1
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Freescale Semiconductor
_DQM
VDDO
_DQM
_SDQ
_OPE
_SDC
VREF DRAM_
_SDQ
_CS0
SD3_
SD3_
SD3_
SD3_
_D28
_D27
_D15
_D10
LK_0
NFB
_D8
_A4
_A0
D5
D6
D4
D0
17
S1
25
S0
1
0
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
SDODT
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
SDCKE
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
SDQS1
SDCLK
SDQS0
SDWE
OPEN
_0_B
CS1
D29
D25
D14
D12
D13
D21
D17
D9
_B
_B
D5
A1
A2
A3
18
0
M_D3
M_D2
DQS3
M_D1
M_A1
M_A1
M_A9
M_A1
M_A1
M_A5
M_A6
DBA2
M_D7
M_D3
M_D1
DQS2
M_D2
M_D1
M_D1
M_D1
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
M_S
M_S
M_S
19
0
4
1
2
3
1
0
3
8
9
6
SDQS3_
SDQS2_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
CALIBR
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
DRAM_
SDBA1
SDBA0
DQM3
ATION
DQM2
RAS
CAS
D31
D22
D20
NC
NC
D6
D4
D2
D0
20
A7
A8
B
B