km41c4000d ETC-unknow, km41c4000d Datasheet - Page 8

• Manufacturer Part Number: km41c4000d
• Description: 4m X 1bit Cmos Dynamic Ram With Fast Page Mode
• Manufacturer: ETC-unknow

KM41C4000D, KM41V4000D
NOTES
10.
11.
12.
13.
14.
15.
16.
1.
2.
3.
4.
5.
6.
7.
8.
9.
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
V
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
Operation within the
If
Assumes that
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
t
characteristics only. If
the duration of the cycle. If
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
Either
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
If
These specifiecations are applied in the test mode.
In test mode read cycle, the value of
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
level.
If
For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycle of burst refresh must be executed within
16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
WCS
OFF(MAX)
IH
IH
t
t
t
RCD
RAD
RASS
(min) and V
(min) and V
,
t
t
RWD
is greater than the specified
is greater than the specified
RCH
100us, then RAS precharge time must use
defines the time at which the output achieves the open circuit condition and are not referenced to output voltage
,
or
t
CWD
t
t
IL
RCD
RRH
IL
(max) and are assumed to be 5ns for all inputs.
(max) are reference levels for measuring timing of input signals. Transition times are measured between
,
t
AWD
must be satisfied for a read cycle.
t
t
RCD
t
RCD
RAD
t
WCS
and
(max).
(max) limit insures that
(max) limit insures that
t
t
t
CPWD
WCS
CWD
(min), the cycle is an early write cycle and the data output will remain high impedance for
are non restrictive operating parameters. They are included in the data sheet as electrical
t
t
t
CWD
RAD
RCD
t
RAC
(min),
(max) limit, then access time is controlled by
(max) limit, then access time is controlled exclusively by
,
t
AA
t
RWD
,
t
t
RAC
t
RAC
CAC
t
t
RPS
(max) can be met.
(max) can be met.
RWD
is delayed by 2ns to 5ns for the specified values. These parameters
instead of
(min),
t
AWD
t
RP
t
.
AWD
t
t
RCD
RAD
(min) and
(max) is specified as a reference point only.
(max) is specified as a reference point only.
t
AA
t
CPWD
.
t
CPWD
t
CAC
(min) then the cycle is a
CMOS DRAM
.
oh
or V
ol
.