x4043s8izt2 Intersil Corporation, x4043s8izt2 Datasheet - Page 8

• Manufacturer Part Number: x4043s8izt2
• Description: Cpu Supervisor With 4kbit Eeprom
• Manufacturer: Intersil Corporation

Figure 5. V
Control Register
The control register provides the user a mechanism for
changing the block lock and watchdog timer settings.
The block lock and watchdog timer bits are nonvolatile
and do not change when power is removed.
The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte
write operation directly to the address of the register
and only one data byte is allowed for each register
write operation. Prior to writing to the control register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register".
Old V
TRIP
New V
CC
Programming Sequence
applied + | Error |
CC
applied =
Error < MDE
8
NO
–
No
Set Higher V
Set V
V
V
TRIP
Output Switches?
TRIP
Present Value ?
Desired V
Actual V
CC
Power-down
Reset Sequence
the Device
X4043, X4045
Ramp V
(RESET)
Desired
V
Execute
Execute
Programming
= desired V
= Error
DONE
TRIP
TRIP
TRIP
| Error | < | MDE |
<
YES
TRIP
YES
CC
Sequence
–
TRIP
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4043/45 will
not acknowledge any data bytes written after the first
byte is entered.
Error > MDE
Old V
Execute Reset V
New V
CC
Sequence
applied – | Error |
+
CC
Let: MDE = Maximum Desired Error
Desired Value
applied =
TRIP
Error = Actual – Desired
MDE
MDE
+
–
Error Range
Acceptable
March 16, 2006
FN8118.2