x5083s8izt2 Intersil Corporation, x5083s8izt2 Datasheet - Page 10
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x5083s8izt2
Manufacturer Part Number
x5083s8izt2
Description
Cpu Supervisor With 8kbit Spi Eeprom
Manufacturer
Intersil Corporation
Datasheet
1.X5083S8IZT2.pdf
(21 pages)
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
• CS must come HIGH at the proper clock count in order to
• When V
latch.
start a nonvolatile write cycle.
are inhibited.
SCK
CS
SO
SI
CC
is below V
High Impedance
SCK
CS
SO
SI
0
TRIP
Read Instruction
1
(1 Byte)
, communications to the device
2
10
0
3
1
4
Read Status
Instruction
FIGURE 6. READ STATUS OPERATION SEQUENCE
2
5
FIGURE 5. READ OPERATION SEQUENCE
3
6
4
7
15 14
5
8
6
9
Byte Address (2 Byte)
X5083
7
SO = Status Reg When no Nonvolatile
20 21 22 23 24 25 26 27 28 29 30
3
Write Cycle
2
1
0
W
D
1
7
W
D
0
6
B
L
2
5
B
L
1
4
Data Out
B
L
0
3
...
...
...
2
1
0
June 15, 2006
FN8127.3