ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 17

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 8-9.
8.7
9248A–RKE–09/11
Data_out (DATA)
Switching the Receiver Back to Sleep Mode
IC_ACTIVE
Bit check
Dem_out
Steady L State Limited DATA Output Pattern After Transmission
Start-up mode
After the end of a data transmission, the receiver remains active. Depending of the bit
Noise_Disable in the OPMODE register, the output signal at pin DATA is high or random noise
pulses appear at pin DATA (see
edge-to-edge time period t
than T
The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON.
When using pin DATA, this pin must be pulled to low by the connected microcontroller for the
period t1.
on page
is not limited; however, exceeding the specified value to prevent erasing the reset marker is
not recommended. Note also that an internal reset for the OPMODE and the LIMIT register is
generated if t1 exceeds the specified values. This item is explained in more detail in the
tion 11. “Configuring the Receiver” on page
achieved by programming bit 1 to “1” during the register configuration. Only one sync pulse
(t3) is issued.
The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time
T
(see
Sleep
Section 14. “Data Interface” on page
elapses after the OFF command. Note that the capacitive load at pin DATA is limited
DATA_min
30). The minimum value of t1 depends on the BR_Range. The maximum value for t1
Figure 8-10 on page 18
.
Bit-check mode
Atmel ATA5723C/ATA5724C/ATA5728C
ee
of the majority of these noise pulses is equal or slightly higher
Section 10. “Digital Noise Suppression” on page
illustrates the timing of the OFF command (see
Receiving mode
32).
25. Setting the receiver to sleep mode via DATA is
t
DATA_min
t
DATA_L_max
Figure 13-2
23). The
Sec-
17