ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 19

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

9. Data Clock
9.1
9248A–RKE–09/11
Generation of the Data Clock
Figure 8-11
to set the receiver back to polling mode using pin POLLING/_ON. The pin POLLING/_ON
must be held to low for the time period t
the delay t
Using the POLLING/_ON command is faster than using pin DATA; however, this requires the
use of an additional connection to the microcontroller.
Figure 8-12
the receiver to receiving mode using the pin POLLING/_ON. The pin POLLING/_ON must be
held to low. After the delay t
regardless of the programmed values for T
held to low, the values for T
ital Noise Suppression” on page
If the receiver is polled exclusively by a microcontroller, T
manent sleep mode). In this case the receiver remains in sleep mode as long as
POLLING/_ON is held to high.
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift
register. Using this data clock, a microcontroller can easily synchronize the data stream. This
clock can only be used for Manchester and Bi-phase coded signals.
After a successful bit check, the receiver switches from polling mode to receiving mode and
the data stream is available at pin DATA. In receiving mode, the data clock control logic (Man-
chester/Bi-phase demodulator) is active and examines the incoming data stream. This is
done, as with the bit check, by subsequent time frame checks where the distance between two
edges is continuously compared to a programmable time window. As illustrated in
on page
are valid (T and 2T).
The limits for T are the same as used with the bit check. They can be programmed in the
LIMIT-register (Lim_min and Lim_max, see
28).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Upper limit of 2T:
(If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it is rounded up.)
The data clock is available, after the data clock control logic has detected the distance 2T
(Start bit) and is issued with the delay t
page
If the data clock control logic detects a timing or logical error (Manchester code violation), as
illustrated in
clock. The receiver remains in receiving mode and starts with the bit check. If the bit check
was successful and the start bit has been detected, the data clock control logic starts again
with the generation of the data clock (see
20).
20, only two distances between two edges in Manchester and Bi-phase coded signals
on3
“Timing Diagram of the OFF Command using Pin POLLING/_ON” illustrates how
“Activating the Receiving Mode using Pin “POLLING/_ON” illustrates how to set
Figure 9-2 on page 20
, the polling mode is active and the sleep time T
Atmel ATA5723C/ATA5724C/ATA5728C
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
Sleep
on1
and N
23).
, the receiver changes from sleep mode to start-up mode
and
Bit-check
on2
Figure 9-3 on page
Delay
Figure 9-4 on page
. After the positive edge on pin POLLING/_ON and
Table 11-10 on page 28
Sleep
is ignored, but not deleted (see
after the edge on pin DATA (see
and N
Bit-check
Sleep
21, it stops the output of the data
Sleep
must be programmed to 31 (per-
21).
. As long as POLLING/_ON is
elapses.
and
Table 11-11 on page
Section 10. “Dig-
Figure 9-1 on
Figure 9-1
19