x45620 Intersil Corporation, x45620 Datasheet
x45620
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x45620 Summary of contents
Page 1
... This allows the power supply and oscillator to stabilize before the processor can execute code. protection A system battery switch circuit compares V with V BATT higher. This provides voltage to external SRAM or other circuits in the event of main power failure. The X45620 can drive 50mA from V device switches to V low OUT ...
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... SDA Operating Temperature Range Part Number 0°C–70°C X45620V20 -40°C–85°C X45620V20I 0°C–70°C X45620V20-2.7 -40°C–85°C X45620V20I-2.7 < V and immediately CC TRIP1 voltage, V2FAIL goes TRIP2 SS (V1MON) OUT BATT and TRIP2 FN8250.0 July 29, 2005 ...
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... V Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1 CC voltage, RESET and LOWLINE go ACTIVE. (V1MON) 3 X45620 Function sense level. When RESET is active communication to the device is interrupt- CC rises above the minimum V CC voltage typically provides the supply voltage necessary to maintain ...
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... V OUT BATT V = 2.8V BATT V , RESET = Open, OUT Note 4 V – 0. -5mA CC OUT V – 0 -50mA CC OUT -250µA OUT 0 3.0mA (5V 1.0mA (3V Power-up -30 mV Power-down, Note 4 4.75 V X45620 2.7 X45620-2.7 2.7 V X45620 1.8 X45620-2.7 , OUT , RE- OUT , FN8250.0 July 29, 2005 ...
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... OUT C Input Capacitance (SDA, SCL, S0, S1, WP) IN EQUIVALENT A.C. LOAD CIRCUIT 1.53kΩ BATT-ON SDA RESET V2FAIL 30pF LOWLINE WDO 5 X45620 (CONTINUED) Limits Min Typ ( Test A.C. TEST CONDITIONS CC Input pulse levels CC Input rise and fall times Input and output timing level 1.53kΩ ...
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... Typical values are for T = 25°C and nominal supply voltage (5V total capacitance of one bus line in pF. Bus Timing SCL t SU:STA SDA IN SDA OUT 6 X45620 Parameter Min 20 + .1Cb 20 + .1Cb 0.6 0 Max stable until the specified operation can be initiated. These parameters are ...
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... The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X45620 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. ...
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... TRIP1 RESET V OUT t VB1 BATT- LOWLINE Timings TRIP1 LOWLINE TRIP1 V BATT 0V V2MON to V2FAIL Timings V2MON 0V V2FAIL 8 X45620 t t PURST PURST t VB2 t RPD RPD2 BATT t RPD BAT 0V V OUT V TRIP RPD V TRIP2 ...
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... BATT Notes: (9) This measurement is from 10% to 90% of the supply voltage. WDT Restart Timing SCL t HD:STA SDA <t WDO Minimum WDT Restart Timing t HIGH SCL t HD:STA SDA WDT Restart 9 X45620 Min 75 400 to TRIP1 100 1000 1000 1 t WDO WDO t t HIGH LOW t SU:STO ...
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... Reset Time Out RST PRINCIPLES OF OPERATION Power-on Reset Application of power to the X45620 activates a Power- on Reset Circuit. This circuit goes active at about 1V and pulls the RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator ...
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... Figure 2. Example System Connection Unregulated 5V Supply Reg Supercap V2MON Provides Early Detection of Power Failure 11 X45620 Operation The device is in normal operation with V through a 5Ω V > when V TRIP is equal ...
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... An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull- up resistor selection graph at the end of this data sheet. 12 X45620 Device Select (S The device select inputs (S the slave address. This allows up to four devices to share a common bus. These inputs can be static or actively driven ...
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... SCL from Master Data Output from Transmitter Data Output fromReceiver Start 13 X45620 Data Stable Data Change Start Bit The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word ...
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... Slave Address Byte High Order Word Address * A14 A13 A12 A11 A10 A9 X45620 Word Address Byte 1 *This bit is 0 for access to the array and 1 for access to the Control Register Low Order Word Address Word Address Byte 0 ...
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... SDA Bus 1 Signals from the Slave 15 X45620 ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be affected. Acknowledge Polling The maximum write cycle time can be significantly reduced using Acknowledge Polling. To initiate ...
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... X45620 Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master ter- ...
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... Prior to initiating a nonvolatile write to the CR, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. 17 X45620 Word Address Word Address Byte 1 Byte 0 0 ...
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... X45620 Write Protect Enable Bit—WPEN (Nonvolatile) The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Control Register control the Program- mable Hardware Write Protect feature. Hardware Write Protection is enabled when the WP pin is connected pin is connected to ground ...
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... Changes made to volatile bits in the Register take effect immediately following the last data bit. 19 X45620 Memory Array Block Protected Block Lock Bits Writes Blocked Writes OK ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 X45620 20-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) ...