lf3330 LOGIC Devices Incorporated, lf3330 Datasheet - Page 6

• Manufacturer Part Number: lf3330
• Description: Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
ration Register 3 set to “1”. When
not cascading, Bit 0 of Configuration
Register 3 should be set to “0”.
It is important to note that the first
multiplier on all cascaded devices
should not be used. This is because
the first multiplier does not have a line
buffer in front of it. The coefficient
value sent to the first multiplier on a
cascaded device should be “0”.
Rounding
The filter output may be rounded by
adding the contents of one of the
sixteen round registers to the filter
output (see Figure 4). Each round
register is 32 bits wide and user-pro-
grammable. This allows the filter’s
output to be rounded to any precision
required. Since any 32-bit value may
be programmed into the round regis-
F
F
CF
IGURE
IGURE
CLK
11-0
LD
CF
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
CLK
11-0
LD
6. C
7. C
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
ADDR
OEFFICIENT
ONFIGURATION
CONFIG REG
1
ADDR
DATA
1
1
COEFFICIENT SET 1
W1
ADDR
COEF
B
SELECT REG
ANK
/C
2
0
ONTROL
DATA
L
OADING
1
W2
ADDR
ters, the device can support complex
rounding algorithms as well as stan-
dard half-LSB rounding. RSL
mines which of the sixteen round reg-
isters are used in the rounding opera-
tion. A value of 0 on RSL
round register 0. A value of 1 selects
round register 1 and so on. RSL
may be changed every clock cycle if
desired. This allows the rounding
algorithm to be changed every clock
cycle. This is useful when filtering
interleaved data. If rounding is not
desired, a round register should be
loaded with 0 and selected as the reg-
ister used for rounding. Round reg-
ister loading is discussed in the LF
Interface
Output Select
The word width of the filter output is
32 bits. However, only 16 bits may be
COEF
R
3
EGISTER
S
7
DATA
EQUENCE
ROUND REGISTER
ADDR
TM
1
W1
section.
DATA
2
COEFFICIENT SET 2
L
COEF
OADING
2
DATA
0
6
3
S
W3
DATA
EQUENCE
3-0
COEF
4
selects
3-0
ADDR
7
3-0
deter-
4
ADDR
DATA
W2
LIMIT REGISTER
3
Vertical Digital Image Filter
COEFFICIENT SET 3
1
sent to DOUT
determines which 16 bits are passed
(see Table 1). There are sixteen select
registers which control the select cir-
cuitry. Each select register is 5 bits
wide and user-programmable. RSL
determines which of the sixteen select
registers are used in the select cir-
cuitry. Select register 0 is chosen by
loading a 0 on RSL
is chosen by loading a 1 on RSL
so on. RSL
clock cycle if desired. This allows the
16-bit window to be changed every
clock cycle. This is useful when filter-
ing interleaved data. Select register
loading is discussed in the LF Inter-
face
Limiting
An output limiting function is pro-
vided for the output of the filter.
COEF
DATA
Video Imaging Products
TM
0
2
section.
DATA
3
3-0
DATA
COEF
15-0
may be changed every
4
. The select circuitry
7
3-0
W4
. Select register 1
W3
9/19/2005–LDS.3330-N
LF3330
3-0
and
3-0