lf3347 LOGIC Devices Incorporated, lf3347 Datasheet - Page 2

• Manufacturer Part Number: lf3347
• Description: High-speed Image Filter With Coefficient Ram
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
with an image resampling se-
quencer. Larger kernels or more
complex functions can be realized
by utilizing multiple devices.
Unrestricted access to all data
ports and addressable coefficient
banks provides the LF3347 with
considerable flexibility in applica-
tions such as digital filters, adap-
tive FIR filters, mixers, and other
similar systems requiring high-
speed processing.
SIGNAL DEFINITIONS
Power
V
+3.3 V power supply. All pins must
be connected.
Clocks
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
CCCLK — Coefficient/Control Clock
When LD is LOW, the rising edge of
CCCLK latches data on CC
device.
Inputs
D1
D1–D4 are the 12-bit registered data
input ports. Data is latched on the
rising edge of CLK.
A
A
coefficient banks feed data to the
multipliers. A
rising edge of CLK. When a new
row address is loaded into the row
address register, data from the
coefficient banks will be latched into
the multiplier input registers on the
next rising edge of CLK.
CC
7-0
7-0
11-0
— Row Address
and GND
determines which row in the
– D4
11-0
— Data Input
7-0
is latched on the
11-0
into the
CC
CC
coefficient banks and control regis-
ters. Data present on CC
latched on the rising edge of CCCLK
when LD is LOW.
Outputs
S
S
output port.
Controls
ENB
The ENB
allow the D
on each clock cycle. When ENB
LOW, data on D
the D
SHIFT
15-0
15-0
T
F
00000
00001
00010
01110
01111
10000
11-0
11-0
ABLE
IGURE
·
·
·
1
— Data Output
is the 16-bit registered data
–ENB
N
(Sign)
(Sign)
–2
–2
— Control/Coefficient Data Input
11 10 9
11 10 9
4-0
is used to load data into the
register on the rising edge of
11
1. O
0
N
1. I
High-Speed Image Filter with Coefficient RAM
2
2
4
(
N
–1
10
N
— Data Input Enables
S
F
F
F
F
F
F
·
·
·
15
16
17
29
30
31
15
registers to be updated
= 1, 2, 3, or 4) inputs
2
2
NPUT
–2
UTPUT
9
N11-0
Data
S
F
F
F
F
F
F
·
·
·
2
14
14
15
16
28
29
30
F
2
S
F
F
F
F
F
F
is latched into
F
ORMATS
2
–9
·
·
·
2
2
Fractional Two's Complement
13
14
15
27
28
29
13
2
ORMATS
Integer Two's Complement
11-0
2
2
1
1
–10
1
is
2
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
2
0
0
–11
0
N
is
CLK. When ENB
D
register and the register contents
will not be changed.
ENBA — Row Address Input Enable
The ENBA input allows the row
address register to be updated on
each clock cycle. When ENBA is
LOW, data on A
the row address register on the rising
edge of CLK. When ENBA is HIGH,
data on A
row address register and the register
contents will not be changed.
OE — Output Enable
When OE is LOW, S
output. When OE is HIGH, S
placed in a high-impedance state.
F
F
F
F
S
F
F
·
·
·
10
22
23
24
N11-0
8
8
9
Video Imaging Products
(Sign)
(Sign)
–2
–2
F
F
F
S
F
F
F
11 10 9
11 10 9
·
·
·
21
22
23
7
8
9
7
is not latched into the D
11
0
2
2
7-0
–1
10
Coefficient
is not latched into the
2
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
2
–2
9
7-0
N
15-0
is latched into
is HIGH, data on
2
2
08/16/2000–LDS.3347-G
2
2
F
F
F
–9
S
F
F
F
2
·
·
·
is enabled for
16
17
18
2
2
3
4
2
2
1
–10
1
1
LF3347
F
F
F
S
F
F
F
·
·
·
15
16
17
2
15-0
1
2
3
1
2
0
–11
0
0
N
F
F
F
S
F
F
F
is
·
·
·
14
15
16
0
0
1
2