lf3370 LOGIC Devices Incorporated, lf3370 Datasheet - Page 13

• Manufacturer Part Number: lf3370
• Description: High-definition Video Format Converter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
F
F
T
A,
B,
C,
D
DESCRIPTION
Coefficient Registers
Configuration Registers
Look-Up Table - Channel ‘A’
Look-Up Table - Channel ‘B’
Look-Up Table - Channel ‘C’
Input Bias Registers - Channel ‘A’
Input Bias Registers - Channel ‘B’
Input Bias Registers - Channel ‘C’
Output Bias Registers - Channel ‘A’
Output Bias Registers - Channel ‘B’
Output Bias Registers - Channel ‘C’
HF0 Count Value
HF1 Count Value
Matrix Mult. RSL Registers - Channel ‘A’
Matrix Mult. RSL Registers - Channel ‘B’
Matrix Mult. RSL Registers - Channel ‘C’
Key Scaler RSL Registers
Half-Band Filter RSL Registers - Channel ‘B’
Half-Band Filter RSL Registers - Channel ‘C’
IGURE
Bypass Data
IGURE
ABLE
DATAPASS
Core Data
Output*
4. C
SECTION
CLK
DEMUX
16.
INPUT
15. B
In this example, the Matrix-Multipler/Key Scaler Section feeds the Half-Band Filter Section. This arrangement is reversible.
*
In this example, the Output Multiplexer is in a mode where the delay through the section is 2 CLK cycles. Only one channel is shown in this example,
however, the other three channels behave in the same manner. The example assumes that the bypass RAM length is set to the length of the core data path.
W1: Bypass data is output to the output port and replaces core data.
W2: Core data is output to the output port and replaces bypass data.
ONFIGURATION
C
D
B
YPASS
0
0
ORE
SECTION
INPUT
BIAS
D
B
B
1
1
B
YPASS
LOCK
D
B
D
2
2
0
SECTION
/C
LUT
ONTROL
D
D
B
D
3
3
1
IAGRAM
MATRIX MULTIPLIER
D
B
D
and KEY SCALER
4
4
2
R
SECTION
ADDRESS RANGE (HEX)
0000 - 0003
0200 - 020A
0600 - 0603
0700 - 0703
0800 - 0803
0900 - 0903
0A00 - 0A03
0B00 - 0B03
0C00
0D00
0E00 - 0E03
0F00 - 0F03
1000 - 1003
1100 - 1103
1200 - 1203
1300 - 1303
EGISTERS
0300
0400
0500
D
D
B
5
5
3
D
B
D
6
6
4
A
13
13
DDRESSING
D
B
D
7
7
5
W1
13
High-Definition Video Format Converter
VARIABLE LENGTH
VARIABLE LENGTH
D
B
B
8
6
BYPASS DELAY
BYPASS DELAY
8
(127 x 13-Bit )
(127 x 13-Bit )
HALF-BAND
SECTION
FILTER
S
D
B
B
UMMARY
9
7
9
D
B
B
10
10
8
D
B
B
11
11
9
13
13
LD is used to enable and disable the
LF Interface™. When LD goes LOW, the
LF Interface™ is enabled for data input.
The first value fed into the interface on
CF
what the interface is going to load (see
Table 4). For example, to load address
Bias Adder Register 2 of the channel B
Output Bias Adder, the first data value
into the LF Interface™ should be 0A02H.
To load RSL Register 1 for the Keyscaler
RSL, the first data value should be 1101H.
The first address value should be loaded
into the interface on the same clock cycle
that latches the HIGH to LOW transition
of LD. The next value(s) loaded into the
interface are the data value(s) which will
be stored in the bank or register defined
by the address value. When loading
coefficient banks, the interface will expect
ten values to be loaded into the device
after the address value. The ten values are
coefficients 0 through 8 and the Keyscale
coefficient. When loading Configuration
or Bias Registers, the interface will expect
one value after the address value. When
loading RSL registers, the interface will
D
B
B
SECTION
12
12
10
Video Imaging Products
12-0
LUT
is an address which determines
D
B
B
13
13
11
SECTION
OUTPUT
D
B
B
BIAS
14
14
12
W2
D
B
D
15
15
13
SECTION
D
B
D
OUTPUT
03/13/2001–LDS.3370-F
16
16
14
MUX
LF3370
D
B
D
17
17
15
W,
X,
Y,
Z