tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 36

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Figure 17. Serial Identification (SID) Register
Figure 18. Configuration (CFG) Register
Figure 19. Power Management (PM) Register
Figure 20. Write Data Serial Load (WDSL) Control Register
PST [1:0]
7
7
7
7
reserved
rsrv
6
6
6
6
rsrv
5
5
5
5
SLE
WDSL [7:0]
4
4
4
4
reserved
rsrv
3
3
3
3
SID [5:0]
2
2
2
2
WIDTH [2:0]
1
1
1
1
TC59YM916BKG24A,32A,32B,40B,32C,40C
PX
0
0
0
0
Serial Identification Register
SADR [7:0]: 00000001
SID [5:0] – Serial Identification field.
This field contains the serial identification value for the device.
The value is compared to the SID [5:0] field of a serial transaction
to determine if the serial transaction is directed to this device. The
serial identification value is set during the initialization sequence.
Configuration Register
SADR [7:0]: 00000010
WIDTH [2:0] – Device interface width field.
SLE - Serial Load enable field.
Power Management Register
SADR [7:0]: 00000011
PX – Power down exit field. (write-one-only read = zero)
PST [1:0] – Power state field (read-only).
Write Data Serial Load Control Register
SADR [7:0]: 00000100
WDSL [7:0]
the serial-to-parallel conversion logic (the “Demux” block of Figure
2). Writing to this register “2x16” times accumulates a full “t
worth of write data. A subsequent WR command (with SLE = 1 in
CFG register in Figure 18) will write this data (rather than DQ data)
to the sense amps of a memory bank. The shifting order of the write
data is shown in Table 10.
000
001
010
011
100
101
0
1
0
1
00
01
10
11
2
2
2
2
2
2
2
2
–
–
–
–
2
2
2
2
2
2
–
–
–
–
, 110
WDSL-path-to-memory disabled
WDSL-path-to-memory enabled
Power down entry do not write zero – use PDN command.
Power down exit – write one to exit
–
–
–
–
–
Power down (with self-refresh).
Active/active-idle
Reserved
Reserved
Reserved
Reserved
×4 device width
×8 device width
×16 device width
–
2
, 111
Writing to this register places eight bits of data into
2
–
2
2
2
2
Reserved
WDSL [7:0] resets to 00000000
CFG [7:0] resets to 00000100
SID [7:0] resets to 00000000
PM [7:0] resets to 00000000
2004-12-15 36/76
Read/write register
Read/write register
Read/write register
Read-only register
Rev 0.1
CC
”
2
2
2
2