tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 72

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Serial Interface Transmit Timing
a magnified view of the pins and only a few clock cycles are shown.
represents a logical one. Timing events are measured to and from the V
measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (t
time (t
maximum delay time (t
(t
information on the SDI input to the SDO output. This combinational propagation delay parameter is t
t
write transaction) because of the accumulated propagation delay through all of the XDR DRAM devices on the
serial interface.
t
Figure 62. Serial Interface Transmit Waveforms
SDO
SCK
CYC,SCK
CYC,SCK
SDI
Figure 62 shows a timing diagram for the serial interface pins of the memory component. This diagram represents
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage
There is one transmit window defined for the serial interface data signal (SDO pins). This window has a
When the memory component is not selected during a serial device read transaction, it will simply pass the
During Initialization, when the serial identification is determined, the SDI−to−SDO path is registered, so the
Q,SI,MIN
OF,SI
20% = V
50% = V
80% = V
t
F,SCK
will need to be increased during a serial read transaction (relative to the t
value can be set to the same value as for serial write transactions. See ”Initialization” on page 45.
) from the next falling edge of the SCK clock signal.
) of the signals are measured from the 20% and 80% points of the full-swing levels.
t
L,SCK
OL,SI
OL,SI
OL,SI
+ 0.2 × (V
+ 0.5 × (V
+ 0.8 × (V
Q,SI,MAX
t
Q,SI,MAX
t
CYC,SCK
OH,SI
OH,SI
OH,SI
t
R,SCK
) from the falling edge of the SCK clock signal and a minimum delay time
Combinational propagation from SDI to
SDO when the device is not selected
during a serial device read transaction.
−V
−V
−V
OL,SI
OL,SI
OL,SI
t
P,SI
)
)
)
t
H,SCK
t
TC59YM916BKG24A,32A,32B,40B,32C,40C
RO
t
Q,SI,MIN
t
FO,SI
REF, RSL
level. Because timing intervals are
CYC,SCK
2004-12-15 72/76
value for a serial
OR,SI
P,SI
) and fall
Rev 0.1
. The
Logic 0
V
80%
V
20%
V
Logic 1
Logic 0
V
80%
V
20%
V
Logic 1
Logic 0
V
80%
V
20%
V
Logic 1
IH,SI
REF,RSL
IL,SI
OH,SI
REF,RSL
OL,SI
IH,SI
REF,RSL
IL,SI