xrt91l31 Exar Corporation, xrt91l31 Datasheet
xrt91l31
Available stocks
Related parts for xrt91l31
xrt91l31 Summary of contents
Page 1
... OCTOBER 2007 GENERAL DESCRIPTION The XRT91L31 is a fully integrated SONET/SDH transceiver for SONET/SDH 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase- Locked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference ...
Page 2
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1 155.52 Mbps Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial- ...
Page 3
... STS12/STS3 RCLK_0 61 60 CDRREFSEL GND 61 VDD3.3 62 MCLK_0 63 62 DLOOP DJA_1/SDI 63 RLOOPS 64 AGND 64 ALOOP P N ART UMBER XRT91L31IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER XRT91L31 ( IEW XRT91L30 24 XRT91L31 ABLE RDERING NFORMATION ...
Page 4
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ........................................................................................................................................... XRT91L31 ...................................................................................................................................... 1 IGURE LOCK IAGRAM OF ......................................................................................................................................................2 FEATURES P C ......................................................................................................................................3 IN ONFIGURATION QFP P O XRT91L31 (T IGURE THE ................................................................................................................................................... 3 ABLE RDERING NFORMATION T C .......................................................................................................... ABLE OF ONTENTS PIN DESCRIPTIONS .......................................................................................................... ....................................................................................................................................................... 6 ABLE ...
Page 5
... OC-12 .................................................................................................................................... 36 IGURE ITTER RANSFER OC-3 ...................................................................................................................................... 36 IGURE ITTER RANSFER OR 4.6.3 JITTER GENERATION................................................................................................................................................ 36 T 19: XRT91L31 O J ABLE PTICAL ITTER T 20: XRT91L31 O J ABLE PTICAL ITTER 5.0 ELECTRICAL CHARACTERISTICS ................................................................................................... RATINGS .................................................................................................................. 38 BSOLUTE AXIMUM T 21 ABLE BSOLUTE AXIMUM ATINGS T 22 ABLE BSOLUTE ...
Page 6
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER PIN DESCRIPTIONS PIN DESCRIPTION AME EVEL RESET LVTTL, LVCMOS STS12/STS3 LVTTL, LVCMOS CMUFREQSEL LVTTL, LVCMOS CDR_BW/VDD LVTTL, LVCMOS ABLE ARDWARE ONTROL P YPE Master Reset Input Active "High." When this pin is pulled "High" , the internal state machines are set to their default state. " ...
Page 7
... RXINP/N is then sampled on the rising edge of externally recovered differential clock XRXCLKIP/N coming from the opti- cal module. "Low" = Internal CDR unit is Enabled "High" = Internal CDR unit is Disabled and Bypassed 7 XRT91L31 D ESCRIPTION CDRAUXREF- Data Rate CLK Frequency CDR uses CMU’s reference clock (see CMUFREQSEL pin) 77 ...
Page 8
... Asserting this control pin "Low" left unconnected, it config- ures TXPCLK_IO to serve as a parallel bus clock input rather than a parallel bus clock output and permits the XRT91L31 to accept the external clock input. Data on the TXDI[7:0] is then sampled at the rising edge of the TXPCLK_IO clock input driven by the framer/mapper device. " ...
Page 9
... TXDI[7:0]. This clock is used by the framer/mapper device to present the TXDI[7:0] data which the XRT91L31 will latch on the rising edge of this clock. This enables the framer/mapper device and the XRT91L31 transceiver synchronization. ...
Page 10
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER TRANSMITTER SECTION AME EVEL REFCLKP LVPECL Diff REFCLKN TTLREFCLK LVTTL, LVCMOS P YPE Reference Clock Input (77.76 MHz or 19.44 MHz) 17 This differential clock input reference is used for the transmit clock multiplier unit (CMU) and clock data recovery (CDR) to provide the necessary high speed clock reference for this device ...
Page 11
... RXPCLKO output. The 8-bit parallel 23 interface is de-multiplexed from the receive serial data input 24 MSB first (RXDO[7]). The XRT91L31 will output the data on the 25 falling edge of RXPCLKO clock ...
Page 12
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER PIN DESCRIPTION AME EVEL CAP1P Analog CAP2P CAP1N Analog CAP2N DLOSDIS LVTTL, LVCMOS LOSEXT SE-LVPECL POWER AND GROUND PIN DESCRIPTION N T AME YPE VDD3.3 PWR 18, 31, 34, 47, 61 AVDD3.3_TX PWR AVDD3.3_RX PWR VDD_PECL PWR ...
Page 13
... STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER Receiver Analog Ground for 3.3V Analog Power Supplies It is recommended that all ground pins of this device be tied together. Power Supply and Thermal Ground It is recommended that all ground pins of this device be tied together. 13 XRT91L31 D ESCRIPTION ...
Page 14
... Clock Input Reference for Clock Multiplier (Synthesizer) Unit The XRT91L31 can accept both a 19.44 MHz or a 77.76 MHz Differential LVPECL clock input at REFCLKP Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed clocks. The REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for SONET systems ...
Page 15
... REV. 1.0.0 2.0 RECEIVE SECTION The receive section of XRT91L31 include the inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero (NRZ) serial data at 622.08 Mbps or 155.52 Mbps through the input interfaces RXIP/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream ...
Page 16
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.2 Recieve Serial Data Input Timing The received High-Speed Serial Differential Data Input must adhere to the set-up and hold time timing specifications below IGURE ECEIVE IGH PEED ERIAL XRXCLKIP XRXCLKIN RXIP RXIN ...
Page 17
... MHz 1 19.44 MHz 0 not referenced by CDR 1 not referenced by CDR ppm in order for the transmitted data rate frequency to 20 ppm. 200 F R EFERENCE REQUENCY EQUIREMENT P ARAMETER 17 XRT91L31 2 CDR O UTPUT F (MH ) REQUENCY Z ( not used 155.52 not used 622.08 not used 155.52 not used 622 ...
Page 18
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. shows the possible internal paths of the recovered clock and data IGURE NTERNAL LOCK AND ATA CLOCK CDRDIS Div by 8 CLOCK ...
Page 19
... Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, and none of the local loopback loops is enabled, the XRT91L31 will automatically force the receive parallel data output to a logic state "0" for the entire duration that a LOS condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data ...
Page 20
... During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L31 is operating in STS-3/ STM-1, the SIPO will convert the 155.52 Mbps serial data input to 19.44 Mbps parallel data output. The SIPO bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0] ...
Page 21
... DLOSDIS and keeping LOSEXT input pin "high." In addition, the user can also assert LOSEXT input pin from the optical module to force an LOS and mute the parallel receiver outputs as well when DLOSDIS is not enabled (LOW), see Figure 7). Figure NTERFACE LOCK XRT91L31 RXDO[7:0] STS-12/STM RXPCLKO STS-3/STM-1 Transceiver 21 XRT91L31 ...
Page 22
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.10 Receive Parallel Data Output Timing The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and hold times shown in Figure 10 ,Table specifications IGURE ECEIVE ARALLEL UTPUT ...
Page 23
... PECL output rise time (20% to 80%) R_PECL t PECL output fall time (80% to 20%) F_PECL t TTL output rise time (10% to 90%) R_TTL t TTL output fall time (90% to 10%) F_TTL TTL AND ECEIVE UTPUTS IMING P ARAMETER 23 XRT91L31 S PECIFICATION NITS 350 ps 350 1.5 ns ...
Page 24
... STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.0 TRANSMIT SECTION The transmit section of the XRT91L31 accepts 8-bit parallel data and converts it to serial Differential LVPECL data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL interface, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Low Voltage Positive-referenced Emitter- Coupled Logic (LVPECL) differential line driver, and Loop Timing modes ...
Page 25
... When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 12, Table 12 and Table 13 IGURE RANSMIT ARALLEL NPUT Transmit Parallel Clock driven by XRT91L31 Device TXPCLK_IO TXDI[7:0] T 12: T ABLE RANSMIT S YMBOL t TXPCLK_IO t Transmit data setup time with respect to TXPCLK_IO TXDI_SU t Transmit data hold time with respect to TXPCLK_IO TXDI_HD ...
Page 26
... When PIO_CTRL pin 48 is asserted "Low," TXPCLK_IO switches into a clock input and the XRT91L31 will now sample data on the transmit parallel bus TXDI[7:0] based on TXPCLK_IO clock input reference coming from the framer/mapper device. The use of the alternate transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing ...
Page 27
... Mbps STS-12/STM 155.52 Mbps STS-3/STM-1 serial data rate 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1) 27 XRT91L31 (STS-12/STM PERATION NITS 12.86 ns 2.0 ns 1.0 ns (STS-3/STM PERATION ...
Page 28
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.6 Clock Multiplier Unit (CMU) and Re-Timer The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS- 12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential LVPECL input REFCLKP/N accepts a clock reference of 77 ...
Page 29
... First, the CDRDIS input pin should be set high. By doing so, the internal CDR is disabled and bypassed and the XRT91L31 will sample the incoming high speed serial data on RXIP/N with the externally recovered receive clock connected to the XRXCLKIP/N inputs. In this state, the receive clock de-jittering and recovery is done externally and fed thru XRXCLKIP/N and the XRT91L31 will sample RXIP/N on the rising edge of XRXCLKIP/N ...
Page 30
... STS-3/STM-1 Transceiver N : Some optical modules integrate AC coupling capacitors within the module coupling is largely specific to OTE system design and optical module of choice. I CDR E NTERNAL OR AN XTERNAL XRT91L31 622.08/ 155.52MHz CMU MUX DATA PISO Retimer to Retimer CLK Div by 8 Clk CLK ...
Page 31
... OCAL OOPBACK Digital Loopback Tx Parallel Input Rx Parallel Output STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER Re-Timer CDR PISO Re-Timer SIPO CDR 31 XRT91L31 Figure 18. Tx Serial Output LVPECL Output Drivers Rx Serial Input LVPECL Input Drivers Tx Serial Output LVPECL Output Drivers LVPECL Input Drivers ...
Page 32
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 4.3 Analog Local Loopback Analog Local Loopback (ALOOP) controls a more comprehensive version of digital local loopback in which the point where the transmit data is looped back is moved all the way back to the high-speed receive I/O. The transmit data from the transmit parallel interface TXDI[7:0] is serialized and presented to the high-speed transmit output TXOP/N using the high-speed 622 ...
Page 33
... REV. 1.0.0 4.5 Eye Diagram The XRT91L31 Eye diagram illustrates the transmit serial output signal integrity and quality IGURE RANSMIT LECTRICAL STS-3/STM-1 4.6 SONET Jitter Requirements SONET equipment jitter requirements are specified for the following three types of jitter. The definitions of each of these types of jitter are given below ...
Page 34
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 23. GR-253 J T IGURE ITTER OLERANCE A 3 Input Jitter Amplitude ( OC-N/STS-N LEVEL T 18: XRT91L31 R ABLE F B REQUENCY AND I NTERFACE (KH ) PTICAL Z OC3/STM1 65 OC12/STM4 250 M ASK slope= -20dB/decade ...
Page 35
... REV. 1.0 IGURE ITTER OLERANCE OR XRT91L31 Jitter Tolerance (OC12) 1000.00 100.00 10.00 1.00 0.10 1E+ IGURE ITTER OLERANCE OR 100.00 10.00 1.00 0.10 1E+00 1E+ LBW and HBW stand for Low Bandwidth and High Bandwidth, respectively. OTE 4.6.2 Jitter Transfer Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency ...
Page 36
... A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter. The jitter attenuator within the XRT91L31 meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the ...
Page 37
... REV. 1.0.0 T 19: XRT91L31 O ABLE EASUREMENT AND ILTER -3dB F REQUENCIES I NTERFACE IGH ASS OW O (KH ) (MH PTICAL Z OC3/STM1 12 1.3 OC12/STM4 20: XRT91L31 O J ABLE PTICAL ITTER EASUREMENT AND ILTER -3dB F REQUENCIES I NTERFACE IGH ASS OW O (KH ) (MH PTICAL ...
Page 38
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Thermal Resistance of QFP Package........ Thermal Resistance of QFP Package........ ESD Protection (HBM)..........................................>2000V T 22: A ABLE S T YMBOL YPE VDD CMOS Digital Power Supply 3.3 VDD PECL I/O Power Supply LVPECL AVDD 3.3V Analog I/O and Power Supply ...
Page 39
... STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 24 ABLE LECTRICAL HARACTERISTICS 0.7 1.1 600 Figure 28 ) VDD - LVPECL 0.9 0 400 1 IDIFF 2 -500 39 XRT91L31 NITS ONDITIONS VDD - V LVPECL 0.9 V VDD - V LVPECL 1.3 1300 mV 187 pull down and 100 line-to-line ter- mination. (see Figure 17 ) VDD - V For LVPECL 0 ...
Page 40
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 28. D IGURE IFFERENTIAL VOLTAGE SWING DEFINITIONS V(+) V(-) V = V(+)-V(-) DIFF NPUT OR OUTPUT FOR CLOCK AND DATA SINGLE 40 REV. 1.0.0 SING LE ...
Page 41
... Note: The control dimension is in millimeters. SYMBOL A 0.072 A1 0.010 A2 0.071 B 0.007 C 0.004 D 0.510 D1 0.390 e L 0.029 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER XRT91L31 INCHES MILLIMETERS MIN MAX MIN MAX 0.096 1.82 2.45 0.020 0.25 0.50 0.087 1.80 2.20 0.011 0.17 0.27 0.009 0.11 0.23 0.530 12.95 13.45 0.398 9.90 10.10 0.0197 BSC 0.50 BSC 0.041 0.73 1.03 0° 7° 0° 7° 41 XRT91L31 ...
Page 42
... XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER REVISION HISTORY EVISION ATE 1.0.0 October 2007 T 25 ABLE EVISION ISTORY ABLE D ESCRIPTION Initial XRT91L31 datasheet release 42 REV. 1.0.0 ...