ak4368 AKM Semiconductor, Inc., ak4368 Datasheet - Page 12

• Manufacturer Part Number: ak4368
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; C
Note 19. Except AC coupling.
Note 20. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
Note 21. Refer to “Serial Data Interface”.
Note 22. BICK rising edge must not occur at the same time as LRCK edge.
MS0529-E-00
Parameter
Master Clock Input Timing
LRCK Timing
MCKO Output Timing (PLL mode)
Serial Interface Timing (Note 21)
Control Interface Timing (3-wire Serial mode)
Frequency (PLL mode)
Pulse Width Low (Note 19)
Pulse Width High (Note 19)
AC Pulse Width (Note 20)
Frequency
Frequency
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
Duty Cycle: Slave Mode
Slave Mode (M/S bit = “0”):
Master Mode (M/S bit = “1”):
CCLK Period
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↑”
SDATA Hold Time
SDATA Setup Time
BICK Period
BICK Pulse Width Low
LRCK Edge to BICK “↑” (Note 22)
BICK “↑” to LRCK Edge (Note 22)
BICK Frequency (BF bit = “1”)
BICK Duty
BICK “↓” to LRCK
SDATA Hold Time
SDATA Setup Time
ground. (Refer to Figure 3.)
Pulse Width High
Pulse Width High
(EXT mode)
(fs=32kHz, PS1-0= “00”)
Master Mode
(BF bit = “0”)
SWITCHING CHARACTERISTICS
Symbol
fCLKO
tBCKH
tMBLR
tCLKH
tBCKL
tCCKL
tCCKH
tCLKL
dMCK
dMCK
tACW
dBCK
tCSW
fCLK
fCLK
tBCK
fBCK
fBCK
tCCK
tCDH
tLRB
tBLR
tSDH
tSDH
tCDS
tCSH
tSDS
tSDS
Duty
Duty
tCSS
fs
L
- 12 -
= 20pF; unless otherwise specified)
0.4/fCLK
0.4/fCLK
11.2896
2.048
0.256
312.5
18.5
min
−50
100
100
200
150
45
40
50
50
50
50
50
50
80
80
40
40
50
50
8
-
-
-
-
-
44.1
64fs
32fs
typ
50
33
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12.288
12.288
max
27
48
55
60
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
[AK4368EG]
Units
2006/07
MHz
MHz
MHz
kHz
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns