ak4368 AKM Semiconductor, Inc., ak4368 Datasheet - Page 43

• Manufacturer Part Number: ak4368
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
2) DAC → Lineout
(1) PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to “1” after PDN pin goes “H”.
(3) The PLL executes when the system clock is input to MCKI.
(4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2.
(5) Table 1. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins.
(6) DACL and DACR bits should be changed to “1” after the PLL is locked.
(7) When the 3D function is used, 3D1-0 bits should be changed to “01” after DACL and DACR bits are changed to “1”.
(8) PMLO bit is changed to “1”.
(9) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(10) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499µs@fs=44.1kHz).
(11) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0529-E-00
MCKI pin
MCKO pin
BICK, LRCK pins
DAC Internal
SDTI pin
3D1-0 bits
(when 3D is used)
Power Supply
PDN pin
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
DACL,
DACR bits
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
State
Figure 35. Power-up/down sequence of DAC and LOUT/ROUT(Don’t care: except Hi-Z)
Don’t care
Don’t care
“00”(3D OFF)
Unstable
Don’t care
(1) >150ns
10H(MUTE)
PD
(Hi-Z)
(2)
>0
(6) >0
00H(MUTE)
Unstable
Unstable
“L”
(3)
(7) >0
(4) ~20ms
(8) >0 (at 3D OFF)
(5)
(8) >0 (at 3D ON)
(9)
(10) GD (11) 1061/fs
Normal Operation
“01”(3D ON)
FFH(0dB)
- 43 -
(10) (11)
Unstable
Don’t care
Don’t care
0FH(0dB)
00H(MUTE)
Unstable
Unstable
(9)
PD
(6) >0
Unstable
(Hi-Z)
“00”
(4) ~20ms
(7) >0
(8) >0 (at 3D OFF)
(8) >0 (at 3D ON)
(9)
Normal Operation
(10)
“01”
(11)
FFH(0dB)
[AK4368EG]
2006/07