ak4372 ETC-unknow, ak4372 Datasheet - Page 19
ak4372
Manufacturer Part Number
ak4372
Description
Dac With Built-in Pll & Hp-amp
Manufacturer
ETC-unknow
Datasheet
1.AK4372.pdf
(62 pages)
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When an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz,19.8MHz, 26MHz
or 27MHz) is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits
frequency is selected between 32fs or 64fs, by BF bit
MS0684-E-02
PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
Table 9. MCKO Frequency (PLL mode, MCKO bit = “1”)
AK4372
Table 10. BICK Output Frequency at Master Mode
BF bit
0
1
MCKI
MCKO
BICK
LRCK
SDATA
PS1
0
0
1
1
Figure 11. PLL Master Mode
256fs/128fs/64fs/32fs
(Table
PS0
0
1
0
1
BICK Frequency
(Table
32fs, 64fs
1fs
9) and the output is enabled by MCKO bit. The BICK output
32fs
64fs
- 19 -
10).
MCKO
256fs
128fs
64fs
32fs
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
MCLK
BCLK
LRCK
SDTO
(default)
DSP or μP
(default)
[AK4372]
2008/12
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