ak4372 ETC-unknow, ak4372 Datasheet - Page 36

• Manufacturer Part Number: ak4372
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: ETC-unknow

2) DAC → Lineout
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
(2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”.
(3) DALL and DARR bits should be changed to “1” after the PMVCM bit is changed to “1”.
(4) PMDAC and PMLO bits should be changed to “1” after DALL and DARR bits is changed to “1”.
(5) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
(6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(7) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499μs@fs=44.1kHz).
(8) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0684-E-02
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
can be stopped. The LOUT/ROUT buffer can operate without these clocks.
Clock Input
PMDAC bit
DAC Internal
SDTI pin
Power Supply
PDN pin
PMVCM bit
DALL,
DARR bits
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
State
Figure 29. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z)
PD(Power-down)
(1) >150ns
10H(MUTE)
(Hi-Z)
(3) >0s
Don’t care
00H(MUTE)
(2)
>0s
(4) >0s
(5)
(6)
(7) GD
Normal Operation
FFH(0dB)
(8) 1061/fs
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(7)
(8)
0FH(0dB)
00H(MUTE)
(6)
Don’t care
Don’t care
(Hi-Z)
PD
(6)
Normal Operation
(7)
(8)
FFH(0dB)
[AK4372]
2008/12