xr16m554 Exar Corporation, xr16m554 Datasheet - Page 25
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xr16m554
Manufacturer Part Number
xr16m554
Description
1.62v To 3.63v Quad Uart With 16-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16M554.pdf
(46 pages)
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REV. 1.0.0
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
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•
•
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
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•
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•
•
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•
•
MCR[2]: Reserved
OP1# is not available as an output pin on the M554. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
4.7
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to HIGH for the transmit and receive data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to LOW for the transmit and receive data.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW.
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
LCR B
X
0
0
1
1
IT
-5 LCR B
X
0
1
0
1
T
ABLE
IT
-4 LCR B
11: P
0
1
1
1
1
ARITY SELECTION
IT
25
-3
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
Forced parity to space, LOW
Force parity to mark, HIGH
P
ARITY SELECTION
Even parity
Odd parity
No parity
XR16M554/554D