xr16m570 Exar Corporation, xr16m570 Datasheet - Page 30
xr16m570
Manufacturer Part Number
xr16m570
Description
1.62v To 3.63v High Performance Uart With 16-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16M570.pdf
(52 pages)
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XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
•
•
4.6
FCR B
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
0
0
1
1
IT
Line Control Register (LCR) - Read/Write
-7
FCR B
T
ABLE
0
1
0
1
IT
Table 10
-6
9: T
FCR B
RANSMIT AND
for parity selection summary below.
0
0
1
1
IT
BIT-1
BIT-2
-5
0
0
1
1
0
1
1
FCR
R
ECEIVE
0
1
0
1
BIT
LENGTH
BIT-0
5,6,7,8
W
-4
6,7,8
0
1
0
1
ORD
5
FIFO T
R
ECEIVE
30
1(default)
L
RIGGER
EVEL
14
4
8
T
RIGGER
S
W
TOP BIT LENGTH
(B
ORD LENGTH
5 (default)
1 (default)
T
IT TIME
ABLE AND
1-1/2
6
7
8
2
T
RIGGER
(
S
T
1(default)
))
RANSMIT
14
L
4
8
EVEL
L
EVEL
S
ELECTION
16L570
C
OMPATIBILITY
REV. 1.0.0