xr16m2752 Exar Corporation, xr16m2752 Datasheet - Page 12

• Manufacturer Part Number: xr16m2752
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16M2752
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal
clock. A bit time is 16 (8) clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and
TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
F
2.10
2.10.1
2.10.2
2.10.3
IGURE
6. T
Transmitter
Transmit Holding Register (THR) - Write Only
Transmitter Operation in FIFO Mode
Transmitter Operation in non-FIFO Mode
RANSMITTER
(EMSR Bit-7)
O
16X or 8X
PERATION IN NON
Clock
Data
Byte
Transmit Shift Register (TSR)
-FIFO M
Transmit
Register
Holding
(THR)
ODE
12
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
S
B
TXNOFIFO1
L
S
B
REV. 1.0.0