xr16m2650im48 Exar Corporation, xr16m2650im48 Datasheet - Page 32

• Manufacturer Part Number: xr16m2650im48
• Description: High Performance Low Voltage Duart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16M2650
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL
is a 16-bit value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must
be enabled via EFR bit-4 before it can be accessed. See
Baud Rate Generator with Fractional Divisor” on page
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See
DLD[7:6]: Reserved
This register contains the device ID (0x06 for XR16M2650). Prior to reading this register, DLL and DLM should
be set to 0x00 (DLD = 0xXX).
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to LOW (disable) before
programming a new setting.
4.10
4.11
4.12
4.13
4.14
Scratch Pad Register (SPR) - Read/Write
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
Enhanced Feature Register (EFR)
DLD[5]
0
0
1
T
ABLE
13: S
Table
AMPLING
DLD[4]
14). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
32
X
0
1
10.
Table 13
R
ATE
S
ELECT
below and
“Section 2.9, Programmable
Table 13
S
AMPLING
16X
8X
4X
R
below.
ATE
REV. 1.0.2