xr16m770il32 Exar Corporation, xr16m770il32 Datasheet
xr16m770il32
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xr16m770il32 Summary of contents
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TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO FEBRUARY 2009 GENERAL DESCRIPTION 1 The XR16M770 (M770 enhanced Universal Asynchronous Receiver and Transmitter (UART) with 64 bytes of transmit and programmable transmit and receive FIFO trigger levels, automatic ...
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... D1 21 24-pin QFN Corner CTS# VCC ORDERING INFORMATION P N ART UMBER XR16M770IL24 XR16M770IL32 XR16M770IB25 24- QFN, 32- QFN 25-BGA P PIN PIN AND DSR# 25 CD# 26 IOR GND VCC 28 9 IOW# ...
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REV. 1.0.0 PIN DESCRIPTIONS Pin Description 24-QFN 32-QFN 25-BGA N AME DATA BUS INTERFACE ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO Pin Description 24-QFN 32-QFN 25-BGA N AME DSR CD RI ANCILLARY SIGNALS XTAL1 8 10 XTAL2 - ...
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REV. 1.0.0 1.0 PRODUCT DESCRIPTION The XR16M770 (M770 high performance single channel UART. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, the M770 channel has 64 bytes of transmit and receive ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The ...
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REV. 1.0.0 2.2 Serial Interface The M770 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422 transceivers www.exar.com ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 5. XR16M770 T S IGURE YPICAL ERIAL DTR# UART NTERFACE ONNECTIONS VCC VCC RTS# DE VCC RE# NC CTS# ...
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REV. 1.0.0 2.3 Device Reset The RESET input resets the internal registers and the serial interface outputs to their default state (see Table 18). An active high pulse of longer than 40 ns duration will be required to activate the ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.6 Crystal Oscillator or External Clock Input The M770 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected ...
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REV. 1.0.0 2.7 Programmable Baud Rate Generator with Fractional Divisor The M770 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver. The prescalers are controlled by a software bit in the MCR register. The MCR register ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES ...
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REV. 1.0.0 2.8 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X internal clock. A ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.8.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever ...
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REV. 1.0 IGURE ECEIVER PERATION IN NON 16X Clock ( DLD[5:4] ) Receive Data Byte and Errors F 11 IGURE ECEIVER PERATION IN 16X lock ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.10 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote ...
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REV. 1.0.0 transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-asserted (LOW), indicating more data may be sent. F 12. A RTS CTS F IGURE ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the ...
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REV. 1.0.0 interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the receiver if the address matches its slave address, otherwise, it does not enable the receiver. If the receiver has ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 13 IGURE NFRARED RANSMIT ATA TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.17 Sleep Mode with Auto Wake-Up and ...
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REV. 1.0.0 an interrupt is pending from any channel. The M770 will stay in the sleep mode of operation until it is disabled by setting IER bit logic 0. A word of caution: owing to the starting up ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.18 Internal Loopback The M770 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All ...
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REV. 1.0.0 3.0 UART INTERNAL REGISTERS The complete register set for the M770 is shown in T ABLE DDRESSES DREV - Device Revision DVID - Device Identification Register 0 0 ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DREV RD Bit DVID DLL RD/WR ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 4.3 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are ...
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REV. 1.0.0 IER[3]: Modem Status Interrupt Enable • Logic 0 = Disable the modem status register interrupt (default). • Logic 1 = Enable the modem status register interrupt. IER[4]: Sleep Mode Enable (requires EFR[ • Logic 0 = ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 4.4.2 Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. ...
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REV. 1.0.0 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and enable the wake up interrupt. They are defined as follows: FCR[0]: TX and ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table-B ...
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REV. 1.0.0 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity Select Parity or no parity ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This condition ...
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REV. 1.0.0 MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and MCR[5]: Xon-Any Enable (requires EFR bit • Logic 0 = Disable Xon-Any ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO LSR[4]: Receive Break Tag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character ...
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REV. 1.0.0 MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input enabled and selected by Auto CTS (EFR bit-7). Auto CTS Flow Control allows starting and stopping of local data transmissions ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 4.12 Enhanced Mode Select Register (EMSR) - Write-only This register replaces SPR (during a Write) and is accessible only when FCTR[ EMSR[1:0]: Receive/Transmit FIFO Level Count When Scratchpad ...
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REV. 1.0.0 EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[6]: LSR Interrupt Mode • Logic 0 = LSR Interrupt Delayed (default). LSR bits ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO DLD[5:4]: Sampling Rate Select These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will double if the 8X mode is ...
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REV. 1.0.0 FC[7:0]: RX/TX FIFO Level Count Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[ Transmitter FIFO (FCTR[ can be read via this register. Reading this register is not recommended when transmitting ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE ...
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REV. 1.0.0 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO REGISTERS DLM, DLL (Both TX and RX) DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FC TRG FCTR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX ...
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REV. 1.0.0 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (32-QFN) Thermal Resistance (24-QFN) Thermal Resistance (25-BGA) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO SEE”POWER-SAVE FEATURE” ON PAGE 21. M770 should NOT be lower than its VCC supply. AC ELECTRICAL CHARACTERISTICS - ...
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REV. 1.0.0 AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay From Center of Start To Reset SRT TXRDY# T Reset Pulse Width RST Bclk Baud Clock ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 17 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CS# IOR# T RDV D0- IGURE ATA US ...
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REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 (Unloading) Bit IER[1] ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 21 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO ...
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REV. 1.0.0 PACKAGE DIMENSIONS (24 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO ) ...
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XR16M770 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL ...
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REV. 1.0.0 PACKAGE DIMENSIONS (25 PIN BGA - 0.8 Seating Plane Note: The control dimension is the millimeter column SYMBOL 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO ...
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... Rev 1.0.0 Added 32-QFN pin package on page 2 to replace the grey block. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...