xr16v2751im Exar Corporation, xr16v2751im Datasheet - Page 24

• Manufacturer Part Number: xr16v2751im
• Description: High Performance Duart With 64-byte Fifo And Powersave Feature
• Manufacturer: Exar Corporation

XR16V2751
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE
SEE”RECEIVER” ON PAGE 15.
SEE”TRANSMITTER” ON PAGE 13.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 1 0
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
XOFF1 RD/WR
XOFF2 RD/WR
T
DREV
FCTR RD/WR
XON1 RD/WR
XON2 RD/WR
N
DVID
DLM
TRG
DLD
EFR
R
DLL
ABLE
FC
AME
EG
9: I
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
RD
RD
RD
EAD
RITE
NTERNAL
/
Enable
RX/TX
Mode
B
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
0
-7
R
EGISTERS
SCPAD
Enable
Swap
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RTS
IT
0
0
-6
Baud Rate Generator Divisor
D
ESCRIPTION
Enhanced Registers
Special
Select
Table
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-1
Bit-5
Bit-5
Bit-5
Bit-5
Trig
IT
0
0
-5
24
MCR[7:5],
IER [7:4],
ISR [5:4],
FCR[5:4],
Enable
.
B
Table
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-0
Bit-4
Bit-4
Bit-4
Bit-4
DLD
Trig
S
IT
0
0
HADED BITS ARE ENABLED WHEN
-4
Direction
Control
RS485
B
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Auto
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
1
-3
RX IR
B
Input
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Soft-
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
Inv.
IT
0
-2
B
ware
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Auto
Hyst
Bit-1
Soft-
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
RTS
Cntl
IT
1
-1
EFR B
B
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Auto
Bit-0
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
RTS
Hyst
Cntl
IT
IT
0
-0
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR=0
EFR[4] = 1
DLM=0x00
DLL=0x00
C
LCR[7]=1
LCR[7]=1
LCR[7]=1
REV. 1.0.1
OMMENT
X
BF