xr16v598 Exar Corporation, xr16v598 Datasheet - Page 43

• Manufacturer Part Number: xr16v598
• Description: 2.25v To 3.6v High Performance Octal Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
MSR [2]: Receiver Disable
This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to
a logic 1, the receiver will operate in one of the following ways:
The receiver can be enabled and will start receiving characters by resetting this bit to a logic 0. The receiver
will operate in one of the following ways:
Any data that is in the RX FIFO can be read out at any time whether the receiver is disabled or not.
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MSR[1]: Reserved
MSR[0]: 9-bit or Multidrop Mode Enable
This bit enables 9-bit or Multidrop mode. See
for complete details.
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This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
FCTR[7:6]: Reserved
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
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FCTR[4]: Infrared RX Input Logic Select
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FCTR [3:0] - Reserved
4.11
4.12
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
Logic 0 = Normal 8-bit mode
Logic 1 = Enable 9-bit or Multidrop mode
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from HIGH to
LOW when finished sending the last stop bit of the last character out of the TSR register. It changes from
LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default).
Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
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If a character is being received at the time of setting this bit, that character will be correctly received. No
more characters will be received.
If the receiver is idle at the time of setting this bit, one character will still be received fully. No more
characters will be received.
If the receiver is idle (RX pin is HIGH) at the time of setting this bit, the next character will be received
normally. It is recommended that the receiver be idle when resetting this bit to a logic 0.
If the receiver is not idle (RX pin is toggling) at the time of setting this bit, the RX FIFO will be filled with
unknown data.
Scratch Pad Register (SPR) - Read/Write
Feature Control Register (FCTR) - Read/Write
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
“Section 2.13, Auto RS-485 Half-duplex Control” on page 18
43
XR16V598