xr16l784iv Exar Corporation, xr16l784iv Datasheet - Page 22

• Manufacturer Part Number: xr16l784iv
• Description: High Performance 2.97v To 5.5v Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for a periodic event. An interrupt may be generated in the INT Register when the timer times out.
It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
TIMERCNTL [0]
TIMERCNLT [1]
TIMERCNTL [2]
TIMERCNTL [3]
TIMERCNTL [7:4]
3.1.2
P
RIORITY
x
1
2
3
4
5
6
7
F
IGURE
TIMERCNTL [3]
TIMERCNTL [1]
TIMERCNTL [2]
TIMERCNTL [0]
TIMERMSB and TIMERLSB
General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (
0
OSC. CLOCK
B
X
0
0
0
0
1
1
1
1
IT
XX-XX-00-00)
15. T
2 B
TMRCK
T
(16-bit Value)
0
0
1
1
0
0
1
1
IT
ABLE
1 B
Logic 0 (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
Logic 0 (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
Logic0 (default) selects re-trigger timer function and logic one selects one-shot (timer function.
Logic 0 (default) selects internal and logic one selects external clock to the timer/counter.
Reserved (defaults to zero).
IMER
0
1
0
1
0
1
0
1
IT
/C
9: UART C
0
Timer Interrupt Enable
Single/Re-triggerable
Clock
Select
Start/Stop
OUNTER CIRCUIT
None
RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the
RX FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR
register.
RXRDY Time-out: Cleared when the FIFO becomes empty.
TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
clear after reading MSR register; Xoff/Xon or special char. detect INT clears after reading
ISR register.
Reserved.
Reserved.
TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL regis-
ter. Reserved in other channels.
1
0
HANNEL
T
ABLE
.
Timer/Counter
10: TIMER CONTROL R
[3:0] I
16-Bit
NTERRUPT
Re-trigger
I
NTERRUPT
22
0
1
Time-out
Single-shot
S
OURCE
S
OURCE
EGISTER
1
0
E
(
S
NCODING AND
)
AND
No Interrupt
Timer Interrupt, Ch-0 INT=7
C
LEARING
C
LEARING
xr
REV. 1.2.2
DEFAULT