xr16c2552ij Exar Corporation, xr16c2552ij Datasheet - Page 22

• Manufacturer Part Number: xr16c2552ij
• Description: 2.97v To 5.5v Dual Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
MCR[3]: OP2# Output
OP2# is available as an output pin on the 2552 when AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is used
to write the state of the modem CD# interface signal. Also see pin descriptions for MF# pins.
MCR[4]: Internal Loopback Enable
MCR[7:5]: Reserved
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
LSR[1]: Receiver Overrun Flag
LSR[2]: Receive Data Parity Error Tag
LSR[3]: Receive Data Framing Error Tag
LSR[4]: Receive Break Tag
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
4.9
Logic 0 = Forces OP2# output to a logic 1 (default).
Logic 1 = Forces OP2# output to a logic 0.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1.
Line Status Register (LSR) - Read Only
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Figure
11.
xr
REV. 1.0.0