xr16c2450ip Exar Corporation, xr16c2450ip Datasheet - Page 3

• Manufacturer Part Number: xr16c2450ip
• Description: Dual Uart With Higher Operating Speed And Lower Access Time
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
DATA BUS INTERFACE
MODEM OR SERIAL I/O INTERFACE
N
IOW#
CSA#
CSB#
IOR#
INTB
INTA
RXA
TXA
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
AME
40-PDIP
P
26
27
28
21
18
14
15
30
29
11
10
IN
8
7
6
5
4
3
2
1
#
44-PLCC
P
29
30
31
24
20
16
17
33
32
13
IN
11
9
8
7
6
5
4
3
2
#
48-TQFP
P
26
27
28
48
47
46
45
44
19
15
10
30
29
IN
11
3
2
1
7
5
#
T
YPE
IO
O
O
O
I
I
I
I
I
I
3
Address data lines [2:0]. These 3 address lines select one
of the internal registers in UART channel A/B during a
data bus transaction.
Data bus lines [7:0] (bidirectional).
Input/Output Read Strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data
byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge
instigates an internal write cycle and the rising edge
transfers the data byte on the data bus to an internal reg-
ister pointed by the address lines.
UART channel A select (active low) to enable UART
channel A in the device for data bus operation.
UART channel B select (active low) to enable UART
channel B in the device for data bus operation.
UART channel A Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTA is set to the active mode and OP2A# output
to a logic 0 when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0 (default).
UART channel B Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTB is set to the active mode and OP2B# out-
put to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0 (default).
UART channel A Transmit Data. If it is not used, leave it
unconnected.
UART channel A Receive Data. Normal receive data input
must idle at logic 1 condition. If it is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
D
ESCRIPTION
2.97V TO 5.5V DUART
XR16C2450