xr17l152im Exar Corporation, xr17l152im Datasheet - Page 10

• Manufacturer Part Number: xr17l152im
• Description: 3.3v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

áç
áç
áç
áç
DISCONTINUED
0x200 - 0x20F
0x210 - 0x2FF
0x300
0x300
0x340 - 0x37F
0x380 - 0x3FF
O
FFSET
A
[A7:A0]
Ox08A
Ox08B
Ox08C
Ox08D
Ox08E
Ox080
Ox081
Ox082
Ox083
Ox084
Ox085
Ox086
Ox087
Ox088
Ox089
Ox08F
Ox090
DDRESS
A
DDRESS
UART channel 1 Regs
Reserved
UART 1 – Read FIFO
UART 1 – Write FIFO
Reserved
UART 1 – Read FIFO
with status
T
ABLE
M
TIMERCNTL
INT2 [23:16]
INT3 [31:24]
EMORY
TIMERMSB
INT1 [15:8]
TIMERLSB
INT0 [7:0]
R
8XMODE
MPIOLVL
MPIOINT
3: D
RESET
TIMER
SLEEP
REGA
REGB
EGISTER
DREV
DVID
T
ABLE
EVICE
S
PACE
2: XR17L152 D
C
ONFIGURATION
Read-only Interrupt [1:0], Reserved [7:2]
Read-only [5:0], Reserved [7:6]
Reserved [7:0]
Reserved [7:0]
Read/Write Timer Control
Reserved
Read/Write Timer LSB
Read/Write Timer MSB
Read/Write
Reserved
Write-only Self clear bits after executing Reset [3:0]
Read/Write Sleep mode [3:0]
Read-only Device revision
Read-only Device identification
Read/Write
Read/Write MPIO interrupt mask
Read/Write MPIO level control
(Table 10
R
Read/Write
Read-Only
Write-Only
Read-Only
EAD
EVICE
/W
&
Table
R
RITE
R
10
EGISTERS SHOWN IN
EAD
C
ONFIGURATION
11)
/W
RITE
D
8/16/24/32
8/16/24/32
8/16/24/32
ATA
C
16/32
OMMENT
W
IDTH
R
EGISTERS
BYTE
First 8 regs are 16550 compatible
64 bytes of RX FIFO data
64 bytes of TX FIFO data
64 bytes of RX FIFO data + LSR
ALIGNMENT
3.3V PCI BUS DUAL UART
C
OMMENT
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x22
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
R
ESET
XR17L152
S
REV. 1.1.0
TATE