xr20v2170 Exar Corporation, xr20v2170 Datasheet - Page 6

no-image

xr20v2170

Manufacturer Part Number
xr20v2170
Description
I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
Manufacturer
Exar Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
xr20v2170IL40-F
Manufacturer:
NXP
Quantity:
260
XR20V2170
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
The V2170 can operate with either an I
the I2C/SPI# input pin. The V2170 can operate with either an I
interface is selected via the I2C/SPI# input pin.
The I
bus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial
clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to
400 kbps. The first byte sent by an I
when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The V2170 responds to each write with an
acknowledge (SDA driven LOW by V2170 for one clock cycle when SCL is HIGH). If the TX FIFO is full, the
V2170 will respond with a negative acknowledge (SDA driven HIGH by V2170 for one clock cycle when SCL is
HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I
transition from LOW to HIGH when SCL is HIGH). See
I
F
F
F
2
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.1.1
C-bus specifications.
IGURE
IGURE
IGURE
SDA
SCL
White block: host to UART
Grey block: UART to host
S
2
C-bus interface is compliant with the Standard-mode and Fast-mode I
3. I
4. M
5. M
CPU Interface
ADDRESS
I
SLAVE
2
C-bus Interface
2
ASTER
ASTER
C S
START condition
TART AND
S
W
R
White block: host to UART
Grey block: UART to host
W
EADS
RITES
S
A
S
F
T
ADDRESS
ROM
TOP
O
SLAVE
REGISTER
ADDRESS
S
LAVE
C
S
ONDITIONS
LAVE
(V2170)
2
2
C-bus master contains a start bit (SDA transition from HIGH to LOW
C-bus interface or an SPI interface. The CPU interface is selected via
(V2170)
W
A
A
S
REGISTER
ADDRESS
ADDRESS
SLAVE
6
Figures 3
2
R
C-bus interface or an SPI interface. The CPU
A
A
-
5
nDATA
below. For complete details, see the
nDATA
2
2
C-bus master is a stop bit (SDA
C-bus specifications. The I
A
A
STOP condition
P
LAST DATA
P
REV. 1.0.0
NA
P
2
C-

Related parts for xr20v2170