71m6534h-igt Maxim Integrated Products, Inc., 71m6534h-igt Datasheet - Page 11

• Manufacturer Part Number: 71m6534h-igt
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

FDS_6533_6534_004
cal assignment of values for the SLOTn_SEL and SLOTn_ALTSEL registers assuming seven time slots
(MUX_DIV = 7) for the processing of three voltage and current phases plus an additional neutral current.
The correlation between signal numbers, CE memory addresses, and analog signals is given in
For the processing of three voltage and current phases in a typical poly-phase meter without neutral
measurement, MUX_DIV is set to 6, and SLOT6_SEL as well as SLOT6_ALTSEL would be empty.
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR,
which is set by FIR_LEN. Each multiplexer state will start on the rising edge of CK32. FIR conversions
require 1, 2, or 3 CK32 cycles. The number of CK32 cycles is determined by FIR_LEN.
1.2.3 A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6533/71M6534. The
resolution of the ADC is programmable using the I/O RAM registers M40MHZ and M26MHZ (see
Initiation of each ADC conversion is controlled by MUX_CTRL as described above. At the end of each ADC
conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX selection.
1.2.4 FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multip-
lexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of
each ADC conversion, the output data is stored into the fixed CE RAM location determined by the multip-
lexer selection as shown in
v1.1
Time Slot
Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV = 7)
0
1
2
3
4
5
6
SLOT0_SEL
SLOT1_SEL
SLOT2_SEL
SLOT3_SEL
SLOT4_SEL
SLOT5_SEL
SLOT6_SEL
SLOT7_SEL
SLOT8_SEL
SLOT9_SEL
Register
Setting for [M40MHZ,
[00], [10] or [11]
M26MHZ]
Table
[01]
© 2007-2009 TERIDIAN Semiconductor Corporation
Regular Slot
Number
3. FIR data is stored LSB justified, but shifted left by eight bits.
Signal
Typical Selections
0
1
2
3
4
5
6
–
–
–
Table 2: ADC Resolution
Signal for
FIR_LEN
ADC
VA
VB
VC
IC
ID
IA
IB
–
–
–
0
1
2
0
1
2
FIR CE Cycles
SLOT0_ALTSEL
SLOT1_ALTSEL
SLOT2_ALTSEL
SLOT3_ALTSEL
SLOT4_ALTSEL
SLOT5_ALTSEL
SLOT6_ALTSEL
SLOT7_ALTSEL
SLOT8_ALTSEL
SLOT9_ALTSEL
Register
138
288
384
186
384
588
71M6533/71M6534 Data Sheet
Alternate Slot
Resolution
Number
18 bits
21 bits
22 bits
19 bits
22 bits
24 bits
Signal
Typical Selections
A
B
1
3
4
5
6
Signal for
Table
Table
TEMP
VBAT
ADC
VC
VA
VB
IC
ID
2).
3.
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