71m6534h-igt Maxim Integrated Products, Inc., 71m6534h-igt Datasheet - Page 33

• Manufacturer Part Number: 71m6534h-igt
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

FDS_6533_6534_004
The MPUs of the 71M6533 and 71M6534 allow seven external interrupts. These are connected as shown
in
T2CON. Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0). The generic
8051 MPU literature states that interrupts 4 through 6 are defined as rising-edge sensitive. Thus, the
hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in
30.
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See Section
1.4.7 Digital I/O
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description
in the
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRISE and PLLFALL have their own enable and
flag bits in addition to the interrupt 6, 4 and enable and flag bits (see
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other
flags, IE_XFER through IE_PB, are cleared by writing a zero to them.
the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the
location of the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them.
v1.1
EX0
EX1
EX2
EX3
EX4
EX5
EX6
EX_XFER
EX_RTC
IEN_WD_NROVF
Table
Flash Memory
Name
30. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in
Interrupt
External
Interrupt Enable
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
0
1
2
3
4
5
6
for more information.
Digital I/O High Priority
Digital I/O Low Priority
FWCOL0, FWCOL1, SPI
CE_BUSY
PLL_OK (rising), PLL_OK (falling)
EEPROM busy
XFER_BUSY, RTC_1SEC or WD_NROVF
SFR A8[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
SFR B8[3]
SFR B8[4]
SFR B8[5]
2002[0]
2002[1]
20B0[0]
section for more detail.
Location
© 2007-2009 TERIDIAN Semiconductor Corporation
Table 31: Interrupt Enable and Flag Bits
Table 30: External MPU Interrupts
Connection
IE0
IE1
IEX2
IEX3
IEX4
IEX5
IEX6
IE_XFER
IE_RTC
WD_NROVF_FLAG
Name
Interrupt Flag
SFR 88[1]
SFR 88[3]
SFR C0[1]
SFR C0[2]
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[1]
20B1[0]
Location
see Section
see Section
falling
falling
rising
falling
falling
Table
Polarity
Interrupt Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (INT 6)
RTC_1SEC interrupt (INT 6)
WDT near overflow (INT 6)
71M6533/71M6534 Data Sheet
31).
1.4.7
1.4.7
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
Table
33