xrt75l00 Exar Corporation, xrt75l00 Datasheet
xrt75l00
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xrt75l00 Summary of contents
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... It independent Receiver, Transmitter Attenuator in a single 52 pin TQFP package. The XRT75L00 can be configured to operate in either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz) modes. The transmitter can be turned off (tri- stated) for redundancy support and for conserving power. The XRT75L00’s differential receiver provides high ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR IGURE LOCK IAGRAM OF THE SDI SDO Serial INT Processor SClk Interface CS RESET HOST/HW Peak Detector STS-1/DS3 E3 REQEN AGC/ RTIP Equalizer RRING SR/DR Local LLB LoopBack TTIP Line Driver TRING MTIP Device ...
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... Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment. JITTER ATTENUATORS The XRT75L00 includes a Jitter Attenuator that meets the Jitter requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards. In addition, the jitter attenuator also meets the Jitter and Wander specifications described in the ANSI T1.105.03b 1997, Bellcore GR-253 and GR-499 standards. ...
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... RANSMIT NTERFACE HARACTERISTICS ECEIVE NTERFACE HARACTERISTICS XRT 75L00 ..................................................................................................................................... 2 IGURE LOCK IAGRAM OF THE J A .................................................................................................................................................... 3 ITTER TTENUATORS XRT75L00 .................................................................................................................................................. 3 IGURE THE ORDERING INFORMATION..................................................................................................................... ABLE OF ONTENTS PIN DESCRIPTIONS (BY FUNCTION) .......................................................................................... .................................................................................................................................................... 4 RANSMIT NTERFACE R I ...................................................................................................................................................... 6 ECEIVE NTERFACE C I ......................................................................................................................................................... 8 ...
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... ESULTS :........................................................................................................................... LEARANCE HRESHOLDS FOR A GIVEN SETTING OF E3 ITU-T G.775 ................................................................................................ 31 AS PER E3 ITU-T G.775................................................................................................. 31 AS PER D LOS : ......................................................................................... 32 ATA WITH CONDITION .................................................................................................................................. 33 DS3/STS-1 ...................................................................................................................... 34 E3 .................................................................................................................................... ......................................................................... 35 REQUENCY ITTER OLERANCE ...................................................................................................................................... 35 ........................................................................................................................................... ITTER TTENUATOR ERFORMANCE ........................................................................................................................................... 37 ............................................................................................................................... 43 LOBAL II XRT75L00 REV. 1.0.2 REQEN (DS3 STS-1 A AND ...................................................................... ...
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... Microprocessor interface). Transmit Negative Data Input If the XRT75L00 is configured in Dual-rail mode, this pin is sampled on the fall- ing or rising edge of TxClk based on the status of the TClkINV pin (in Hardware mode) or the status of the control bit in the Channel Register (in HOST mode). ...
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... E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR D ESCRIPTION Transmit Ring Output The XRT75L00 uses this pin along with TTIP to transmit a bipolar signal to the line using a 1:1 transformer. Transmit Line Build-Out Enable/Disable Select This input pin is used to enable or disable the Transmit Line Build-Out circuit. ...
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... In Hardware mode, setting this input pin “High” configures the Receiver Sec- tion to invert the RxClk output signals and outputs the recovered data via RPOS and RNEG on the falling edge of RxClk the XRT75L00 is configured in HOST mode, this pin functions as CS OTE input pin (please refer to the pin description for Microprocessor Interface). ...
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... In Hardware mode: Tie the pin SR/DR (pin 22) “High” to configure the XRT75L00 in Single Rail mode and tie “Low” to configure in Dual Rail mode. In HOST mode: XRT75L00 can be configured in Single Rail or Dual Rail by set- ting or clearing the bit in the block control register. Line Code Violation Indicator ...
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... N : This pin is internally pulled down. OTE Clock out put: When the Single Frequency Mode is selected, a low jitter clock will be out put. The frequency of this clock depends on whether the XRT75L00 is configured DS3 or STS-1 mode. 8 REV. 1.0.2 ...
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... N : OTES 1. This pin is internally pulled down 2. This pin is ignored and may be tied to GND if the XRT75L00 is configured to operate in HOST mode. Single-Rail/Dual-Rail Select: Setting this “High” configures both the Transmitter and Receiver to operate in Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In Single-rail mode, Transmit input at TNData should be grounded. Setting this “ ...
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... AMI all “1’s” pattern onto the line. The frequency of this “1’s” pattern is determined by TxClk OTES 1. This input pin is ignored if the XRT75L00 is operating in the HOST Mode and should be tied to GND. 2. Analog Loopback and Remote Loopback have priority over request. 3. This pin is internally pulled down. MUTE-upon-LOS Enable Input or Interrupt Ouput: In Hardware Mode, setting this pin “ ...
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... N : This input pin is ignored and may be connected to GND if the XRT75L00 OTE is operating in the HOST Mode. Remote Loop-back This input pin along with LLB configures different Loop-Back modes This input pin is ignored and should be connected to GND if the OTE XRT75L00 is operating in the HOST Mode ...
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... INT/LOSMUT I/O D ESCRIPTION Register Reset: Setting this input pin "Low" causes the XRT75L00 to reset the contents of the Command Registers to their default settings and default operating configuration N : This pin is internally pulled up. OTE INTERRUPT Output: This pin functions as Interrupt Output for Serial Interface. A transition to “Low” ...
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... Jitter Attenuator Select: In Hardware Mode setting this pin “High” selects the Jitter Attenuator in the Transmit path and setting “Low” selects in Receive path This pin is internally pulled down. OTE 13 XRT75L00 Operation 16 bit FIFO 32 bit FIFO Disable Jitter Attenuator Disable Jitter ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR ANALOG POWER AND GROUND IGNAL AME YPE 3 TxAVDD **** 10 RxAVDD **** 32 RefAVDD **** 5 TxAGND **** 13 RxAGND **** 34 RefAGND **** 45 JaAVDD **** 43 JaAGND **** DIGITAL POWER AND GROUND IGNAL AME YPE 31 DVDD **** 35 DGND **** 52 DVDD **** 49 DGND **** D ESCRIPTION Transmitter Analog VDD 3.3 V ± 5% Receiver Analog VDD 3.3 V ± ...
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... The Digital inputs and outputs are TTL 5V compliant. E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR ABLE BSOLUTE AXIMUM ATINGS MIN -0.5 -0.5 -65 - LECTRICAL HARACTERISTICS ARAMETER = XRT75L00 MAX UNITS COMMENTS 6.0 V Note 1 5+0.5 V Note 1 100 mA Note 1 150 0 Note linear airflow 0 ft./min ...
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... TPData Transmit TxNEG TNData Logic Block TxLineClk TxClk Exar E3/DS3/STS-1 LIU RANSMITTER ERMINAL NPUT t FTX t t TSU THO E3 DS3 STS-1 16 REV. 1.0.2 XRT75L00 ( - ) DUAL RAIL DATA T IMING MIN TYP MAX UNITS 34.368 MHz 44.736 MHz 51.84 MHz ...
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... ATA OUTPUT AND CODE VIOLATION TIMING t t RRX FRX t LCVO PARAMETER Duty Cycle E3 DS3 STS-1 A ULSE MPLITUDE TEST CIRCUIT FOR TTIP TPData TNData TxClk Rext RefAGND TRing 17 XRT75L00 MIN TYP MAX UNITS 34.368 MHz 44.736 MHz 51.84 MHz 2.5 ...
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... E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 3.0 LINE SIDE CHARACTERISTICS: 3.1 E3 line side parameters: The XRT75L00 meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation at the secondary of the transformer. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure ...
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... E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR RANSMIT UTPUT ULSE EMPLATE FOR ST S-1 Pulse T emplate Time STS ABLE ULSE ASK QUATIONS LOWER CURVE 0 UPPER CURVE 0 0 XRT75L00 SONET STS-1 A PPLICATIONS Lower Curve Upper Curve N A ORMALIZED MPLITUDE - 0.03 T sin -- - 1 + --------- - – 0.03 2 0.18 - 0.03 0.03 T sin -- - 1 + ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 5: STS-1 T ABLE RANSMITTER AND P ARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio ...
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... E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T 6: DS3 ABLE ULSE ASK QUATIONS LOWER CURVE 0.5 1 UPPER CURVE 0.5 1 0.08 + 0.407 ECEIVER INE IDE PECIFICATIONS ECEIVER LINE SIDE INPUT CHARACTERISTICS 21 XRT75L00 N A ORMALIZED MPLITUDE - 0. sin -- - 1 + --------- - – 0.03 2 0.18 - 0.03 0. sin -- - 1 + --------- - + 0 ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR F 10 IGURE ICROPROCESSOR ERIAL CS SClk SDI R High Z SDO F 11 IGURE IMING IAGRAM FOR THE SCLK SDI R/W CS SCLK SDO Hi-Z Hi-Z SDI I S NTERFACE TRUCTURE ...
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... Falling Edge of SClk to SDO Invalid Time 30 t Rising edge High Rise/Fall time of SDO Output 32 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR NTERFACE IMINGS XRT75L00 =3.3V± AND LOAD NITS ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 4.0 THE TRANSMITTER SECTION: The Transmitter Section accepts TTL/CMOS level signals from the Terminal Equipment in the selectable data formats. In Single-Rail or un-encoded Non-Return-to-Zero (NRZ) input data via TPData pin while the TNData pin must be grounded. The NRZ or Single-Rail mode is selected when the SR/DR input pin is “High” (in Hardware Mode) or bit 0 of the control register is “ ...
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... Encoder and Decoder is enabled only in Single-Rail mode. E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR XRT75L00 ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 4 RANSMIT ULSE HAPER The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark Inversion (AMI) pulse that meet the industry standard mask template requirements for STS-1 and DS3. See Figure 8 and Figure 9 ...
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... This feature provides support for Redundancy the XRT75L00 is configured in Host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a “1” to the TxON control bit transfers the control to TxON pin. ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 5.0 THE RECEIVER SECTION This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses. 5.1 AGC/Equalizer The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate ...
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... DS3/STS-1 EST ET UP FOR T S E3. EST ET UP FOR ATTENUATOR NTERFERENCE ARGIN EST ( TTENUATION NTERFERENCE 29 XRT75L00 Cable Simulator DUT XRT75L00 Test Equipment Cable Simulator DUT XRT75L00 Test Equipment ESULTS T OLERANCE -14 dB -18 dB -17 dB -16 dB -16 dB -16 dB -15 dB -15 dB ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 5.2 Clock and Data Recovery: The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the following two modes: ...
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... Maximum Cable Loss for E3 LOS Signal Must be Cleared LOS Signal may be Cleared or Declared LOS Signal Must be Declared E3 ITU-T G.775. AS PER Line Signal is Restored Time Range for 255 UI LOS Declaration G.775 Compliance 31 XRT75L00 10 UI 255 Time Range for G.775 LOS Clearance Compliance ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 5.4.2.1 Muting the Recovered Data with LOS condition: When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the ExClk pin and output this clock on the RxClk output. The data on the RPOS and RNEG pins can be forced to zero by pulling the LOSMUT pin “ ...
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... Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22 shows the jitter tolerance curve as per GR-499 specification along with the measured performance for the device. E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR : Data DUT DUT XRT75L00 XRT75L00 Clock 33 XRT75L00 Error Error Detector Detector ...
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... IGURE NPUT ITTER OLERANCE FOR 64 10 1.5 0.3 0.1 The Figure 11 below shows the jitter amplitude versus the modulation frequency for various standards. F DS3/STS 0 JITTER FREQUENCY (kHz) 34 REV. 1.0.2 GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT75L00 20 100 ITU-T G.823 XRT75L00 800 ...
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... In general, the jitter is measured over a band of frequencies. 6.4 Jitter Attenuator: An advanced crystal-less jitter attenuator is included in the XRT75L00. The jitter attenuator uses the internal reference clock. In Host mode, by clearing or setting the JATx/Rx bit in the control register selects the jitter attenuator either in the Receive or Transmit path ...
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... KBITS G.823 34368 ETSI-TBR-24 44736 GR-499, Cat I GR-499, Cat II GR-253 CORE 51840 GR-253 CORE The jitter attenuator within the XRT75L00 meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure 24 IGURE ITTER RANSFER EQUIREMENTS AND ...
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... The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the processor. When the XRT75L00 is configured in Host mode, the following input pins,TxLEV, TAOS, RLB, LLB, E3, STS-1/ DS3, REQEN, JATx/Rx, JA0 and JA1 are disabled and must be connected to ground. ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR DDRESS ARAMETER ( AME 7 0x08- 0x1F 0x20 Interrupt Enable- Global (read/write) 0x21 Interrupt Status (read only) 0x22- Reserved 0x2F 0x30 PRBS Error Count MSB (MSB) 0x31 PRBS Error Count MSB (LSB) 0x32-0x37 ...
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... Attenuator is disabled. PRBSIE Writing a “1” to this bit enables the PRBS bit error interrupt. Writing a “1” to this bit enables the PRBS error- counter saturation interrupt. When the PRBS error counter reaches 0xFFFF, an interrupt will be gener- ated. 39 XRT75L00 D EFAULT ALUE IN 0 ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR A DDRESS YPE IT OCATION ( 0x02 Reset D0 Upon Read CNT_SATIS 0x03 Read D0 Only 16 ABLE EGISTER AP ESCRIPTION S D YMBOL ESCRIPTION DMOIS This bit is set to “1” every time a DMO status change has occurred since the last cleared interrupt ...
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... RxClkINV Writing a “1” to this bit configures the Receiver to out- put RPOS/RNEG data on the falling edge of RxClk. ALOSDIS Writing a “1” to this bit disables the ALOS detector. DLOSDIS Writing a “1” to this bit disables the DLOS detector. 41 XRT75L00 D EFAULT ALUE IN ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR A DDRESS YPE IT OCATION ( 0x06 R 0x07 R 16 ABLE EGISTER AP ESCRIPTION S D YMBOL ESCRIPTION SR/DR Writing a “1” to this bit configures the Receiver and Transmitter into Single-Rail (NRZ) mode. ...
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... The source level interrupt status register is read to determine the cause of interrupt. Reserved PRBS error counter MSB [15:8] PRBSlsb PRBS error counter LSB [7:0] Reserved PRBS Holding Register Reserved Chip_id This read only register contains device id. 43 XRT75L00 D EFAULT ALUE IN LOBAL D EFAULT V ...
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... Analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path. XRT75L00 can be configured in Analog Loopback either in Hardware mode via the LLB and RLB pins or in Host mode via LLB and RLB bits in the channel control registers. ...
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... RPOS DECODER RNEG 1 if enabled 2 if enabled and selected in either Receive or Transmit path E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR TIMING CONTROL DATA & CLOCK RECOVERY TIMING CONTROL DATA & CLOCK RECOVERY 45 XRT75L00 TTIP Tx TRING RTIP Rx RRING TTIP Tx TRING RTIP Rx RRING ...
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... XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 8.2.3 REMOTE LOOPBACK: With Remote loopback activated as shown in Figure 28,the receive data on RTIP and RRING is looped back after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit timing. The receive data is also output via the RPOS and RNEG pins. ...
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... A1 0.002 0.006 0.05 A2 0.053 0.057 1.35 B 0.009 0.015 0.22 C 0.004 0.008 0.09 D 0.465 0.480 11.80 D1 0.390 0.398 9.90 e 0.0256 BSC 0.65 BSC L 0.018 0.030 0.45 0° 7° 0° 7° typ 7° typ aaa - 0.003 - 47 XRT75L00 PERATING EMPERATURE ANGE -40°C to +85° MAX 1.60 0.15 1.45 0.38 0.20 12.20 10.10 0.75 7° 0.08 ...
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... XRT75L00 REVISION HISTORY 1.0.1 Removed evaluation schematic. 1.0.2 Changed the Device ID to reflect the correct value. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...