xrt75l06 Exar Corporation, xrt75l06 Datasheet
xrt75l06
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xrt75l06 Summary of contents
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR MARCH 2004 GENERAL DESCRIPTION The XRT75L06 is a six channel fully integrated Line Interface Unit (LIU) for E3/DS3/STS-1 applications. The LIU incorporates 6 independent Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 FEATURES RECEIVER On chip Clock and Data Recovery circuit for high input jitter tolerance Meets E3/DS3/STS-1 Jitter Tolerance Requirement Detects and Clears LOS as per G.775 Receiver Monitor mode handles flat ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR F 2. XRT75L06 BGA IGURE IN PACKAGE V ) IEW (See pin list for pin names and function OTTOM XRT75L06 XRT75L06 REV. 1.0 ...
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... Figure 13. Transmit Path Block Diagram ........................................................................................................ 24 3 RANSMIT IGITAL NPUT Figure 14. Typical interface between terminal equipment and the XRT75L06 (dual-rail data) ....................... 24 Figure 15. Transmitter Terminal Input Timing ................................................................................................. 25 Figure 16. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 25 3 ............................................................................................................................................ 26 RANSMIT LOCK 3.3 B3ZS/HDB3 E ...
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... T 11 ABLE ELECTING THE ICROPROCESSOR Figure 34. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 42 6 ICROPROCESSOR NTERFACE T 12: XRT75L06 M ABLE ICROPROCESSOR 6 SYNCHRONOUS AND YNCHRONOUS T 13 ABLE SYNCHRONOUS IMING Figure 35. Asynchronous µP Interface Signals During Programmed I/O Read and Write Operations ........... 45 Figure 36. Synchronous µ ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 Figure 37. Interrupt process ............................................................................................................................ 47 6.2.1 Hardware Reset: ................................................................................................................................. ABLE EGISTER AP AND ABLE EGISTER AP ESCRIPTION T 17 ABLE EGISTER AP AND ABLE EGISTER AP ESCRIPTION 7.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 56 ...
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... Transmit Clock Input for TPOS and TNEG - Channel 5: The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm. The duty cycle can be 30%-70%. By default, input data is sampled on the falling edge of TxCLK. 4 XRT75L06 REV. 1.0.3 Transmitter Status OFF OFF OFF ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR TRANSMIT INTERFACE EAD IGNAL AME YPE F2 TNEG_0 I P2 TNEG_1 G15 TNEG_2 R17 TNEG_3 H3 TNEG_4 K15 TNEG_5 F3 TPOS_0 I N3 TPOS_1 F16 TPOS_2 P15 TPOS_3 G2 TPOS_4 J15 TPOS_5 D1 TTIP_0 O N1 TTIP_1 ...
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... If configured in Single Rail mode then Line Code Violation will be output. Receive Input - Channel 0: Receive Input - Channel 1: Receive Input - Channel 2: Receive Input - Channel 3: Receive Input - Channel 4: Receive Input - Channel 5: These pins along with RTIP receive the bipolar line signal from the remote DS3/ E3/STS-1 Terminal. 6 XRT75L06 REV. 1.0.3 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR RECEIVE INTERFACE EAD IGNAL AME YPE A6 RTIP_0 I U6 RTIP_1 A13 RTIP_2 U13 RTIP_3 A10 RTIP_4 U10 RTIP_5 D ESCRIPTION Receive Input - Channel 0: Receive Input - Channel 1: Receive Input - Channel 2: Receive Input - Channel 3: ...
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... Low jitter clock output for each channel based on the mode selection (E3,DS3 or STS-1) if the CLKOUTEN_n bit is set in the control register. This eliminates the need for a separate clock source for the framer OTES 1. The maximum drive capability for the clockouts is 16 mA. 2. This clock out is available both in SFM and non-SFM modes. 8 XRT75L06 REV. 1.0.3 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR CONTROL AND ALARM INTERFACE EAD IGNAL AME YPE B7 MRING_0 I R6 MRING_1 C14 MRING_2 R14 MRING_3 C6 MRING_4 D14 MRING_5 B8 MTIP_0 I R7 MTIP_1 C13 MTIP_2 R13 MTIP_3 C7 MTIP_4 D13 MTIP_5 C5 DMO_0 ...
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... Processor Mode Select: When this pin is tied “High”, the microprocessor is operating in synchronous mode which means that clock must be applied to the PCLK (pin 55). Tie this pin “Low” to select the Asynchronous mode. An internal clock is pro- vided for the microprocessor interface. 10 XRT75L06 REV. 1.0.3 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR MICROPROCESSOR INTERFACE EAD IGNAL AME YPE T3 RDY O U3 INT O B4 ADDR[ ADDR[1] B3 ADDR[2] C4 ADDR[3] C3 ADDR[4] C2 ADDR[5] D3 ADDR[6] D4 ADDR[7] N4 D[0] I/O P3 D[1] P4 D[2] P5 D[3] R5 D[4] R4 D[5] R3 D[6] R2 D[7] D ESCRIPTION Ready Acknowledge This pin must be connected to VDD via 3 k ...
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... Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 1 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 2 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 3 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 4 **** Analog 3.3 V ± 5% VDD - Jitter attenuator Channel 5 **** Analog GND - Jitter Attenuator Channel 0 **** Analog GND - Jitter Attenuator Channel 1 **** 12 XRT75L06 REV. 1.0.3 ESCRIPTION ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR ANALOG POWER AND GROUND EAD IGNAL AME F14 JaAGND_2 J14 JaAGND_3 H4 JaAGND_4 H14 JaAGND_5 C10 AGND R10 AGND H9 AGND J9 AGND K9 AGND N15 REFAVDD M15 REFGND D YPE Analog GND - Jitter Attenuator Channel 2 ...
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... Receiver Digital GND - Channel 0 Receiver Digital GND - Channel 1 Receiver Digital GND - Channel 2 Receiver Digital GND - Channel 3 Receiver Digital GND - Channel 4 Receiver Digital GND - Channel 5 VDD 3.3 V ± 5% VDD 3.3 V ± 5% VDD 3.3 V ± 5% VDD 3.3 V ± 5% VDD 3.3 V ± 5% Digital GND Digital GND Digital GND 14 XRT75L06 REV. 1.0.3 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR DIGITAL POWER AND GROUND EAD IGNAL AME YPE M4 JaDGND_1 **** P7 DGND **** H8 DGND **** J8 DGND **** K8 DGND **** H10 DGND **** J10 DGND **** K10 DGND **** D ESCRIPTION Digital GND Digital GND Digital GND Digital GND Digital GND ...
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... E3Clk N : For one input clock reference, the single frequency mode should be used. OTE NPUT LOCK IRCUITRY DS3Clk E3Clk Clock Synthesizer 0 Processor ODE ITHOUT SING Clock Synthesizer Processor 16 XRT75L06 REV. 1.0 RIVING THE ICROPROCESSOR CLKOUT_n LOL_n SFM CLKOUT_n LOL_n ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 2.0 THE RECEIVER SECTION The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by cable loss or flat loss according to industry specifications. Once data is recovered processed and presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC ...
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... Lock condition is declared by toggling RLOL_n output pin “High” or setting the RLOL_n bit to “1” in the control register. Also, the clock output on the RxClk_n pins are the same as the reference channel clock. D IAGRAM Peak Detector Slicer AGC/ Equalizer LOS Detector 18 XRT75L06 REV. 1.0.3 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 2.5 LOS (Loss of Signal) Detector 2.5.1 DS3/STS-1 LOS Condition A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line. When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is cleared when the detected average pulse density is greater than 33% for 175 ± ...
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... LOS Signal Must be Cleared LOS Signal may be Cleared or Declared LOS Signal Must be Declared E3 ITU-T G.775. AS PER Actual Occurrence Line Signal of LOS Condition is Restored Time Range for 10 UI 255 UI LOS Declaration G.775 Time Range for Compliance LOS Clearance 20 XRT75L06 REV. 1.0 255 G.775 Compliance ...
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... Pattern Generator PRBS F 11 IGURE NTERFERENCE ARGIN Sine Wave N Generator 17.184mHz Signal Source PRBS T S DS3/STS-1 EST ET UP FOR Attenuator Cable Simulator T S E3. EST ET UP FOR Attenuator 1 Attenuator 2 Cable Simulator 21 DUT XRT75L06 Test Equipment DUT XRT75L06 Test Equipment ...
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... ODE E3 DS3 STS NTERFERENCE ARGIN EST ABLE ENGTH TTENUATION feet 225 feet 450 feet 0 feet 225 feet 450 feet 22 XRT75L06 REV. 1.0.3 R ESULTS I T NTERFERENCE OLERANCE Equalizer “IN” -17 dB -14 dB -15 dB -15 dB -14 dB -15 dB -14 dB -14 dB ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 2.5.5 Muting the Recovered Data with LOS condition: When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “ ...
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... YPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE Terminal Equipment (E3/DS3 or STS-1 Framer) D IAGRAM Tx Jitter Timing Pulse Attenuator Control Shaping Tx Control TxPOS TPData Transmit TxNEG TNData Logic Block TxLineClk TxClk Exar E3/DS3/STS-1 LIU 24 XRT75L06 REV. 1.0.3 TxClk_n HDB3/ B3ZS TxPOS_n MUX Encoder TxNEG_n TxON Channel n XRT75L06 ( - ) DUAL RAIL DATA ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 F IGURE t RTX TxClk TPData or TNData TTIP or TRing SYMBOL PARAMETER TxClk Duty Cycle TxClk Frequency E3 DS-3 STS-1 t TxClk Rise Time (10% to 90%) RTX t TxClk Fall Time (10% to 90%) FTX t TPData/TNData to TxClk falling set up time ...
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... V pulses. This avoids the introduction of DC component into the analog signal. ( ENCODER AND DECODER ARE DISABLED XRT75L06 REV. 1.0 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 F 19. HDB3 E F IGURE NCODING ORMAT TClk TPDATA 1 0 Line Signal 1 3 RANSMIT ULSE HAPER The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark Inversion (AMI) pulse that meets the industry standard mask template requirements for STS-1 and DS3 ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 3.5 E3 line side parameters The XRT75L06 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0 ABLE RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS PARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (Measured at secondary of the transformer) Transmit Output Pulse Amplitude Ratio ...
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... T 0.26 < < 0. RANSMIT UTPUT ULSE EMPLATE FOR ST S-1 Pulse T emplate Time STS ABLE ULSE ASK QUATIONS LOWER CURVE 0.5 1 UPPER CURVE 0 XRT75L06 REV. 1.0.3 SONET STS-1 A PPLICATIONS Lower Curve Upper Curve N A ORMALIZED MPLITUDE - 0.03 · sin -- - 1 + ---------- - 0.03 – 2 0.18 - 0.03 0.03 · sin -- - 1 + ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0 STS ABLE RANSMITTER INE P ARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width ...
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... M E ABLE ULSE ASK QUATIONS LOWER CURVE 0.5 1 UPPER CURVE 0.5 1 0.08 + 0.407 IDE UTPUT AND ECEIVER INE M 0.65 0.90 10.10 0.90 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 900 0. and V = 3.3V ± 5 XRT75L06 REV. 1.0 ORMALIZED MPLITUDE - 0.03 · sin -- - 1 + ---------- - 0.03 – 2 0.18 - 0.03 0.03 · sin -- - 1 + ---------- - + 0.03 2 0.34 -1.84[T-0.36 (GR-499) ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 3.6 Transmit Drive Monitor This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on the line or a defective line driver. To activate this function, connect MTIP_n pins to the TTIP_n lines via a 270 ...
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... DS3/STS-1 Jitter Tolerance Requirements Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 26 shows the jitter tolerance curve as per GR-499 specification. Data DUT XRT75L06 Clock 34 XRT75L06 REV. 1.0.3 Error Detector ...
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... As shown in the Figures above, in the jitter tolerance measurement, the dark line indicates the minimum level of jitter that the E3/DS3/STS-1 compliant component must tolerate. Table 8 below shows the jitter amplitude versus the modulation frequency for various standards. F DS3/STS 0 JITTER FREQUENCY (kHz) 35 GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT75L06 20 100 ITU-T G.823 XRT75L06 800 ...
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... Jitter Attenuator An advanced crystal-less jitter attenuator per channel is included in the XRT75L06. The jitter attenuator requires no external crystal nor high-frequency reference clock. By clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter attenuator either in the Receive or Transmit path on per channel basis ...
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... KBITS G.823 34368 ETSI-TBR-24 44736 GR-499, Cat I GR-499, Cat II GR-253 CORE 51840 GR-253 CORE The jitter attenuator within the XRT75L06 meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure 28 IGURE ITTER RANSFER EQUIREMENTS AND ...
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... Any subsequent single bit error insertion must be done by first writing a “0” to INSPRBS bit and followed by a “1”. Figure 29 shows the status of RNEG/LCV pin when the XRT75L06 is configured in PRBS mode PRBS mode, the device is forced to operate in Single-Rail Mode. ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 5.2 LOOPBACKS The XRT75L06 offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback modes. 5.2.1 ANALOG LOOPBACK In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs RTIP_n and RRing_n as shown in Figure 30 ...
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... Input signals on TxClk, TxPOS and TxNEG are ignored during Remote loopback. OTE F 32 IGURE EMOTE OOPBACK TxCLK HDB3/B3ZS TxPOS ENCODER TxNEG RxCLK HDB3/B3ZS RxPOS DECODER RxNEG TIMING Tx CONTROL DATA & CLOCK Rx RECOVERY TIMING Tx CONTROL DATA & CLOCK Rx RECOVERY 40 XRT75L06 REV. 1.0.3 TTIP TRing RTIP RRing TTIP TRing RTIP RRing ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 5.3 TRANSMIT ALL ONES (TAOS) Transmit All Ones (TAOS) can be set by setting the TAOS_n control bits to “1” in the Channel control registers. When the TAOS is set, the Transmit Section generates and transmits a continuous AMI all “1’s” pattern on TTIP_n and TRing_n pins ...
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... MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT75L06 supports a parallel interface asynchronously or synchronously timed to the LIU. The mi- croprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface mode is shown in Table 11 ...
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... Read/Write access Chip Select Input This active low signal selects the microprocessor interface of the XRT75L06 LIU and enables Read/Write operations with the on-chip register locations Read Signal This active low input functions as the read signal from the local pin is pulled “ ...
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... After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this to inform the µP that the data has been written into the internal register location, and that it is ready for the next command. 6. The CS input pin must be pulled "High" before a new command can be issued. D ESCRIPTION 44 XRT75L06 REV. 1.0.3 input pin WR ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 F 35. A µP I IGURE SYNCHRONOUS NTERFACE READ OPERATION t 0 Addr[7:0] Valid Address CS D[7: RDY T ABLE S P YMBOL ARAMETER t Valid Address to CS Falling Edge Falling Edge to RD Assert Assert to RDY Assert ...
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... Valid Data for Readback YNCHRONOUS IMING PECIFICATIONS 5ns period 46 XRT75L06 REV. 1.0.3 I EAD AND RITE PERATIONS WRITE OPERATION Valid Address Data Available to Write Into the LIU NITS - ns, see note 1 - ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 F 37. I IGURE NTERRUPT PROCESS YES ERROR CONDITION OCCURS Interrupt enable NO bits at 0x60 and 0xn1 set? YES Interrupt status bits at 0x61 and 0xn2 set. Interrupt Generated INT pin goes "Low" Interrupt Service ...
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... EGISTER AP AND IT AMES D B ATA TxON_5 TxON_4 TxON_3 RxON_5 RxON_4 RxON_3 INTEN_5 INTEN_4 INTEN_3 INTEN_2 INTEN_1 INTEN_0 INTST_5 INTST_4 INTST_3 INTST_2 INTST_1 INTST_0 Reserved Chip version number 48 XRT75L06 REV. 1.0.3 ITS TxON_2 TxON-1 TxON_0 RxON_2 RxON_1 RxON_0 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 T ABLE A R DDRESS EGISTER T YPE ( AME 0x00 R/W APS # 1 0x08 R/W APS # 2 0x60 R/W Interrupt Enable 0x61 ROR Interrupt Status 0x62 - 0x6D 0x6E R Device _ id 0x6F R Version Chip_version This read only register contains chip version number ...
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... ATA ALOS_n TxMON_n INSPRBS _n DLOSDIS ALOSDIS _n _n PRBSEN_ RLB_n N_n 0 Reserved DFLCK_n PNTRST_ Bit 14 Bit 13 Bit 12 Bit 6 Bit 5 Bit 4 50 XRT75L06 REV. 1.0 0,1,2,3,4,5) EGISTERS N ITS FL_n RLOL_n RLOS_n DMO_n Reserved TAOS_n TxCLKINV TxLEV_n _n RxCLKIN LOSMUT_ RxMON_n REQEN_ V_n n LLB_n E3_n ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 T ABLE A R DDRESS EGISTER T BIT# YPE ( AME D0 D1 0x01 (ch 0) R/W Interrupt 0x11 (ch 1) Enable 0x21 (ch 2) (source D2 0x31 (ch 3) level) 0x41 (ch 4) 0x51 ( D6- 0x02 (ch 0) Reset ...
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... DS/STS-1 applications. PRBSLS_n This bit is set when the PRBS detector has been enabled and it is not in sync with the incoming data pattern. Once the sync is achieved, it will be cleared. Reserved 52 XRT75L06 REV. 1.0.3 HANNEL N D EFAULT V ALUE ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 T ABLE A R DDRESS EGISTER T BIT# YPE ( AME D0 D1 0x04 (ch 0) R/W Transmit D2 0x14 (ch 1) Control 0x24 (ch 2) 0x34 (ch 3) 0x44 ( 0x54 ( D7- 0x05 (ch 0) R/W Receive 0x15 (ch 1) ...
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... RCLK to generate TCLK will cause an unstable condition and should be avoided. CLKOUTE Set this bit to enable the CLKOUTs on a per channel N_n basis. The frequency of the output clock is depen- dent on the configuration of the channels, either E3, DS3 or STS-1. Reserved 54 XRT75L06 REV. 1.0.3 HANNEL N D EFAULT V ALUE ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 T ABLE A R DDRESS EGISTER T BIT# YPE ( AME D0 0x07 (Ch 0) R/W Jitter 0x17 (Ch 1) Attenuator 0x27 (Ch 2) 0x37 (ch 3) 0x47 (ch 4) 0x57 ( D7-D5 18 EGISTER AP ESCRIPTION S D YMBOL ...
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... ATINGS MIN MAX -0.5 6.0 -0.5 5.5 100 -65 150 - 2000 20 LECTRICAL HARACTERISTICS ARAMETER = XRT75L06 REV. 1.0.3 UNITS COMMENTS V Note 1 V Note 1 mA Note 1 0 Note linear airflow 0 ft./min C 0 linear air flow 0ft/min C/W (See Note 3 below) level EIA/JEDEC JESD22-A112-A ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR T ABLE P ARAMETER Turns Ratio Primary Inductance Isolation Voltage Leakage Inductance P N ART UMBER PE-68629 PE-65966 PE-65967 T 3001 TG01-0406NS TTI 7601-SM TransPower TRANSFORMER VENDOR INFORMATION Pulse Corporate Office 12220 World Trade Drive ...
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... Halo Electronics Corporate Office P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6165 Email: info@haloelectronics.com Website: http://www.haloelectronics.com Transpower Technologies, Inc. Corporate Office Park Center West Building 9805 Double R Blvd, Suite # 100 Reno, NV 89511 (800)500-5930 or (775)852-0140 Email: info@trans-power.com Website: http://www.trans-power.com 58 XRT75L06 ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR P N ART UMBER XRT75L06IB PACKAGE DIMENSIONS - 217 LEAD BGA PACKAGE ORDERING INFORMATION P ACKAGE 217 Lead BGA ( mm) BOTTOM VIEW (A1 corner feature is mfger option) Note: The control dimension is in millimeter. ...
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... XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REVISIONS R D EVISION ATE P1.0.0 Original P1.0.2 Renamed the pins DJA and FSS. Included the Clock out and Clock enable func- tion for the Single Frequency Mode. Changed the TxON pin from internal pull down to pull up.Changed the operation of P1 ...