xrt75l06d Exar Corporation, xrt75l06d Datasheet
xrt75l06d
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xrt75l06d Summary of contents
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER APRIL 2005 GENERAL DESCRIPTION The XRT75L06D is a six channel fully integrated Line Interface Unit (LIU) for E3/DS3/STS-1 applications. The LIU incorporates 6 independent Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.4 FEATURES RECEIVER • On chip Clock and Data Recovery circuit for high input jitter tolerance • Meets E3/DS3/STS-1 Jitter Tolerance Requirement • Detects and Clears LOS as per G.775 • Receiver Monitor mode handles flat loss with 6 dB cable attenuation • ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 2. XRT75L06D BGA IGURE IN PACKAGE V ) IEW (See pin list for pin names and function OTTOM XRT75L06D XRT75L06D REV. 1.0 ...
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... HRESHOLDS FOR A GIVEN SETTING OF E3 ITU-T G.775............................................................................................ 20 AS PER E3 ITU-T G.775. ........................................................................................... 20 AS PER S DS3/STS-1................................................................................................ 21 EST ET UP FOR S E3.............................................................................................................. 21 EST ET UP FOR R ........................................................................................................................... 22 ESULTS ................................................................................................. 23 ................................................................................................................................ 24 IAGRAM XRT75L06D ( T ........................................................................................................................ 25 NPUT IMING ORMAT NCODER AND ECODER ARE NABLED ........................................................................................................................................... ............................................................................. 26 ENCODER AND DECODER ARE DISABLED .......................................................................................................................................... REV. 1.0.4 M ...
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... NES 6.0 MICROPROCESSOR INTERFACE BLOCK ......................................................................................... ABLE ELECTING THE ICROPROCESSOR F 34 IGURE IMPLIFIED LOCK IAGRAM OF THE 6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ............................................................................ 43 T 12: XRT75L06D M ABLE ICROPROCESSOR 6.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION............................................................................. 44 F 35. A µP I IGURE SYNCHRONOUS NTERFACE T 13 ABLE SYNCHRONOUS IMING F 36. S µ ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER IGURE HE YTE ORMAT OF THE F 42 IGURE HE YTE ORMAT OF THE F 43 IGURE LLUSTRATION OF THE YTE F 44 IGURE N LLUSTRATION OF ELCORDIA F 45 "B -O IGURE IMPLIFIED IT RIENTED STS-1 SPE ............................................................................................................................................................. 64 AN 7.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE " ...
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... DDRESS - HANNEL DDRESS OCATION HANNEL DDRESS OCATION HANNEL DDRESS OCATION ....................................................................................................................................... 95 : .............................................................................................................................. 95 217 L BGA .................................................................. 98 EAD PACKAGE IV XRT75L06D 06.................................................... 87 0E................................................. .................................................. 07.................................. 0F..................................... ..................................... 07................................... 0F............................... 88 OCATION ............................... 88 OCATION 07................................... 88 ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER PIN DESCRIPTIONS ( BY FUNCTION TRANSMIT INTERFACE EAD IGNAL AME YPE T15 TxON_0 I Transmitter ON Input - Channel 0: R16 TxON_1 Transmitter ON Input - Channel 1: R15 TxON_2 Transmitter ON Input - Channel 2: N14 TxON_3 Transmitter ON Input - Channel 3: ...
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... J17 TRING_5 Transmit Ring Output - Channel 5: These pins along with TTIP transmit bipolar signals to the line using a 1:1 trans- former. D ESCRIPTION : OTES 1. These input pins are ignored and must be grounded if the Transmitter Section is configured to accept Single-Rail data from the Terminal Equipment. 5 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER RECEIVE INTERFACE S IGNAL EAD YPE N AME A2 RxCLK_0 O Receive Clock Output - Channel 0: U2 RXCLK_1 Receive Clock Output - Channel 1: A17 RxCLK_2 Receive Clock Output - Channel 2: U17 RxCLK_3 Receive Clock Output - Channel 3: D8 ...
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... Receive Input - Channel 1: A13 RTIP_2 Receive Input - Channel 2: U13 RTIP_3 Receive Input - Channel 3: A10 RTIP_4 Receive Input - Channel 4: U10 RTIP_5 Receive Input - Channel 5: These pins along with RRING receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal. D ESCRIPTION 7 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER CLOCK INTERFACE EAD IGNAL AME YPE E15 E3CLK I E3 Clock Input (34.368 MHz ± 20 ppm): If any of the channels is configured in E3 mode, a reference clock 34.368 MHz is applied on this pin. N G16 ...
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... Receive Loss of Signal - Channel 3: B11 RLOS_4 Receive Loss of Signal - Channel 4: R8 RLOS_5 Receive Loss of Signal - Channel 5: This output pin toggles "High" if the receiver has detected a Loss of Signal Con- dition. D ESCRIPTION : This pin is internally pulled up. OTE : This pin is internally pulled up. OTE 9 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER CONTROL AND ALARM INTERFACE C9 RLOL_0 O Receive Loss of Lock - Channel 0: T8 RLOL_1 Receive Loss of Lock - Channel 1: D12 RLOL_2 Receive Loss of Lock - Channel 2: R11 RLOL_3 Receive Loss of Lock - Channel 3: C11 RLOL_4 Receive Loss of Lock - Channel 4: ...
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... OTES 1. This pin will remain asserted “Low” until the interrupt is serviced. 2. This pin must be conneced to VDD via 3 kΩ ± 1% resistor. ADDRESS BUS: 8 bit address bus for the microprocessor interface DATA BUS: 8 bit Data Bus for the microprocessor interface 11 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER ANALOG POWER AND GROUND EAD IGNAL AME YPE E2 TxAVDD_0 **** N2 TxAVDD_1 **** E16 TxAVDD_2 **** N16 TxAVDD_3 **** J2 TxAVDD_4 **** J16 TxAVDD_5 **** D2 TxAGND_0 **** M2 TxAGND_1 **** D16 TxAGND_2 **** M16 TxAGND_3 **** H2 TxAGND_4 **** H16 TxAGND_5 **** A4 RxAVDD_0 **** U4 RxAVDD_1 **** ...
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... M15 REFGND **** D ESCRIPTION Analog GND - Jitter Attenuator Channel 2 Analog GND - Jitter Attenuator Channel 3 Analog GND - Jitter Attenuator Channel 4 Analog GND - Jitter Attenuator Channel 5 Analog GND Analog GND Analog GND Analog GND Analog GND Analog 3.3 V ± 5% VDD - Reference Reference GND 13 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DIGITAL POWER AND GROUND EAD IGNAL AME YPE F1 TxVDD_0 **** L1 TxVDD_1 **** F17 TxVDD_2 **** L17 TxVDD_3 **** K1 TxVDD_4 **** K17 TxVDD_5 **** C1 TxGND_0 **** P1 TxGND_1 **** C17 TxGND_2 **** P17 TxGND_3 **** G1 TxGND_4 **** G17 TxGND_5 **** B5 RxDVDD_0 **** T5 RxDVDD_1 **** ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.4 DIGITAL POWER AND GROUND EAD IGNAL AME YPE M4 JaDGND_1 **** P7 DGND **** H8 DGND **** J8 DGND **** K8 DGND **** H10 DGND **** J10 DGND **** K10 DGND **** D ESCRIPTION Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND 15 XRT75L06D ...
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... DS3Clk E3Clk N : For one input clock reference, the single frequency mode should be used. OTE NPUT LOCK IRCUITRY DS3Clk E3Clk Clock Synthesizer 0 µProcessor ODE ITHOUT SING Clock Synthesizer µProcessor 16 XRT75L06D D M RIVING THE ICROPROCESSOR CLKOUT_n LOL_n SFM CLKOUT_n LOL_n ...
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... Whether using E3, DS-3 or STS-1, the LIU requires the same bill of materials, see Figure IGURE ECEIVE INE NTERFACE DS-3/E3/STS-1 IAGRAM Clock & Data Jitter Slicer MUX Recovery Attenuator LOS Detector C ONNECTION 1:1 Receiver 37.5Ω 37.5Ω 0.01µF RLOS_n 17 XRT75L06D RxClk_n HDB3/ B3ZS RxPOS_n Decoder RxNEG/LCV_n RLOS_n Channel n RTIP_n 75Ω RRing_n ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 2.2 Adaptive Gain Control (AGC) The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak detector provides feedback to the equalizer before slicing occurs ...
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... AND AND PPLICATIONS IGNAL EVEL TO ECLARE ETTING D EFECT 0 < 75mVpk 0 < 45mVpk 1 < 120mVpk 1 < 55mVpk 0 < 120mVpk 0 < 50mVpk 1 < 125mVpk 1 < 55mVpk 19 XRT75L06D ) ALOS ALOS IGNAL EVEL TO LEAR D EFECT > 130mVpk > 60mVpk > 45mVpk > 180mVpk > 170mVpk > 75mVpk > 205mVpk > 90mVpk ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 2.5.3 E3 LOS Condition: If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the LOS condition is detected. Loss of signal is defined as no transitions for 10 to 255 consecutive zeros. No transitions is defined as a signal level between 15 and 35 dB below the normal. This is illustrated in Figure 8. ...
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... F 11 IGURE NTERFERENCE ARGIN Sine Wave N Generator 17.184mHz Signal Source PRBS T S DS3/STS-1 EST ET UP FOR Attenuator ∑ Cable Simulator T S E3. EST ET UP FOR Attenuator 1 Attenuator 2 ∑ Cable Simulator 21 XRT75L06D DUT XRT75L06D Test Equipment DUT XRT75L06D Test Equipment ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T ABLE M C ODE E3 DS3 STS NTERFERENCE ARGIN EST ABLE ENGTH TTENUATION feet 225 feet 450 feet 0 feet 225 feet 450 feet 22 xr REV. 1.0.4 R ESULTS I T NTERFERENCE OLERANCE Equalizer “ ...
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... B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n output pins to indicate line code violation. D ECEIVER ATA OUTPUT AND CODE VIOLATION TIMING t RRX FRX t LCVO 23 XRT75L06D MIN TYP MAX UNITS 34.368 MHz 44 ...
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... YPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE Terminal Equipment (E3/DS3 or STS-1 Framer) D IAGRAM Tx Jitter Timing Pulse Attenuator Control Shaping Tx Control TxPOS TPData Transmit TxNEG TNData Logic Block TxLineClk TxClk Exar E3/DS3/STS-1 LIU 24 xr REV. 1.0.4 TxClk_n HDB3/ TxPOS_n B3ZS MUX Encoder TxNEG_n TxON Channel n XRT75L06D ( - ) DUAL RAIL DATA ...
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... NRZ D IGURE INGLE AIL OR Data TPData TxClk 15 RANSMITTER ERMINAL NPUT t FTX t t TSU THO ATA ORMAT NCODER AND ECODER ARE XRT75L06D T IMING MIN TYP MAX UNITS 34.368 MHz 44.736 MHz 51.84 MHz NABLED 0 ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 17 IGURE UAL AIL ATA ORMAT Data TPData TNData TxClk 3.2 Transmit Clock The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS ...
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... DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit EST IRCUIT R1 TTIP(n) TPData(n) 31.6Ω +1% TNData(n) R2 TxClk(n) TRing(n) 31.6Ω XRT75L06D 75Ω 1:1 ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 3.5 E3 line side parameters The XRT75L06D line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure ...
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... Signal level to Declare Loss of Signal Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time N : The above values are OTE 0.90 0.95 12.5 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0. and V = 3.3 V± 5 XRT75L06D MIN TYP MAX UNITS 1.00 1. 1.00 1.05 14.55 16.5 ns 0.02 0. ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 22. B GR-253 CORE T IGURE ELLCORE 1.2 1 0.8 0.6 0.4 0 IME IN NIT NTERVALS < < -0.85 T -0.38 < < -0.38 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.26 < < 0. RANSMIT UTPUT ULSE EMPLATE FOR ST S-1 Pulse T emplate Time STS-1 P ...
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... IDE UTPUT AND ECEIVER INE 0.65 0.90 0.90 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0. and V = 3.3 V ± 5 DS3 B EMPLATE FOR AS PER ELLCORE D S3 Pulse T em plate Tim XRT75L06D (GR-253) IDE NPUT PECIFICATIONS NITS 0.75 0. 1.00 1. 8.6 9.65 10 ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER IME IN NIT NTERVALS < < -0.85 T -0.36 < < -0.36 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.36 < < 0. DS3 T L ABLE RANSMITTER INE P ARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) ...
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... To permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a “1” to the TxON_n control bits transfers the control to TxON pin TTIP(n) TRing(n) TPData(n) TNData(n) R1 TxClk(n) MTIP(n) 270Ω R2 MRing(n) 270Ω 33 XRT75L06D R1 31.6Ω +1% R3 75Ω R2 1:1 31.6Ω ...
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... DS3/STS-1 Jitter Tolerance Requirements Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 26 shows the jitter tolerance curve as per GR-499 specification. Data DUT XRT75L06D Clock 34 xr REV. 1.0.4 Error ...
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... As shown in the Figures above, in the jitter tolerance measurement, the dark line indicates the minimum level of jitter that the E3/DS3/STS-1 compliant component must tolerate. Table 8 below shows the jitter amplitude versus the modulation frequency for various standards. F DS3/STS 0 JITTER FREQUENCY (kHz) 35 XRT75L06D GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT75L06D 20 100 ITU-T G.823 XRT75L06D 800 ...
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... Jitter Attenuator An advanced crystal-less jitter attenuator per channel is included in the XRT75L06D. The jitter attenuator requires no external crystal nor high-frequency reference clock. By clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter attenuator either in the Receive or Transmit path on per channel basis ...
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... KBITS G.823 34368 ETSI-TBR-24 44736 GR-499, Cat I GR-499, Cat II GR-253 CORE 51840 GR-253 CORE The jitter attenuator within the XRT75L06D meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure 28 IGURE ITTER RANSFER EQUIREMENTS AND ...
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... Any subsequent single bit error insertion must be done by first writing a “0” to INSPRBS bit and followed by a “1”. Figure 29 shows the status of RNEG/LCV pin when the XRT75L06D is configured in PRBS mode PRBS mode, the device is forced to operate in Single-Rail Mode. ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.4 5.2 LOOPBACKS The XRT75L06D offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback modes. 5.2.1 ANALOG LOOPBACK In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs RTIP_n and RRing_n as shown in Figure 30 ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 5.2.2 DIGITAL LOOPBACK When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n & TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in Figure 31. ...
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... Figure 33. TAOS does not operate in Analog loopback or Remote loopback modes, however will function in Digital loopback mode (TAOS) IGURE RANSMIT LL NES TxCLK HDB3/B3ZS TxPOS ENCODER TxNEG RxCLK HDB3/B3ZS RxPOS DECODER RxNEG TIMING Tx CONTROL TAOS DATA & CLOCK Rx RECOVERY 41 XRT75L06D TTIP Transmit All 1's TRing RTIP RRing ...
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... MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT75L06D supports a parallel interface asynchronously or synchronously timed to the LIU. The mi- croprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface mode is shown in Table 11 ...
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... I/O Bi-Directional Data Bus for register "Read" or "Write" Operations. Addr[7:0] I Eight-Bit Address Bus Inputs The XRT75L06D LIU microprocessor interface uses a direct address bus. This address bus is provided to permit the user to select an on-chip register for Read/Write access Chip Select Input This active low signal selects the microprocessor interface of the XRT75L06D LIU and enables Read/Write operations with the on-chip register locations ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 6 SYNCHRONOUS AND YNCHRONOUS Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The synchronous mode requires an input clock (PCLK used as the microprocessor timing reference. Read and Write operations are described below. ...
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... D P IGNALS URING ROGRAMMED t 0 Valid Data for Readback SYNCHRONOUS IMING PECIFICATIONS XRT75L06D I EAD AND RITE PERATIONS WRITE OPERATION Valid Address Data Available to Write Into the LIU NITS - ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 36. S µP I IGURE YNCHRONOUS NTERFACE READ OPERATION PCLK t 0 Addr[7:0] Valid Address CS D[7: RDY T ABLE S P YMBOL ARAMETER t Valid Address to CS Falling Edge Falling Edge to RD Assert Assert to RDY Assert ...
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... Interrupt status bits at 0x61 and 0xn2 set. Interrupt Generated INT pin goes "Low" Interrupt Service Routine reads the status register at 0x61 Interrupt Service Routine reads the status register at 0xn2 Interrupt is being serviced. NO Interrupt Pending ? 47 XRT75L06D INT pin goes "High" Normal Operation ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 6.2.1 Hardware Reset: The hardware reset is initiated by pulling the RESET pin “Low” for a minimum of 5 µ s. After the RESET pin is released, the register values are put in default states DDRESS ARAMETER ...
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... Chip_id This read only register contains device id AND IT AMES HANNEL ATA PRBSER PRBSERI CNTIE_n E_n PRBSER PRBSERI CNTIS_n S_n 49 XRT75L06D LOBAL D EFAULT V ALUE 0 Transmitter Status OFF OFF OFF 01010110 ( = 0,1,2,3,4,5) EGISTERS N ITS FLIE_n ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T 17 ABLE EGISTER A P DDRESS ARAMETER ( AME 7 0x03 (ch 0) Alarm Status Reserved PRBSLS_n DLOS_n 0x13 (ch 1) (read only) 0x23 (ch 2) 0x33 (ch 3) 0x43 (ch 4) 0x53 (ch 5) 0x04 (ch 0) Transmit ...
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... FIFO reaches (or leaves) a limit condition. This limit condition is defined as the FIFO being within two counts of full or empty. PRBSERIS This bit is set when the PRBS error occurs. _n PRBSERC This bit is set when the PRBS error count register NTIS_n saturates. Reserved 51 XRT75L06D HANNEL N D EFAULT V ALUE ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T ABLE A R DDRESS EGISTER T BIT# YPE ( AME 0x03 (ch 0) Read Alarm Sta- 0x13 (ch 1) Only tus 0x23 (ch 2) 0x33 (ch 3) 0x43 ( 0x53 ( 18 EGISTER ...
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... DLOSDIS are normally used in diagnostic mode. Normal operation of DS3 and STS-1 would have ALOS disabled. DLOSDIS_ This bit disables the digital LOS detector. This would n normally be disabled in E3 mode function of the level of the input. Reserved 53 XRT75L06D HANNEL N D EFAULT V ALUE ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER T ABLE A R DDRESS EGISTER T BIT# YPE ( AME 0x06 (Ch 0) R/W Block Con- 0x16 (Ch 1) trol 0x26 ( 0x36 (ch 3) 0x46 (ch 4) 0x56 ( 18 EGISTER AP ESCRIPTION ...
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... FIFO. All existing FIFO data is lost. DFLCK_n Set this bit to “1” to disable fast locking of the PLL. This helps to reduce the time for the PLL to lock to incoming frequency when the Jitter Attenuator switches to narrow band. Reserved 55 XRT75L06D HANNEL N D EFAULT V ALUE 0 Mode 16 bit FIFO ...
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... Similar things are done outside of North America. In this case, this DS3 or E3 signal is routed to a PTE, where it is asynchronously mapped into an SDH signal. This asynchronously mapped DS3 or E3 signal is then transported across the SDH network (from one PTE to the PTE at the other end of the SDH network). Once 56 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER this SDH signal arrives at the remote PTE, this DS3 or E3 signal will then be extracted from the SDH signal, and will be output to some other DS3/E3 Terminal Equipment for further processing. Figure 38 presents an illustration of this approach to transporting DS3 data over a SONET Network F 38 ...
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... In order to be able to describe how a DS3 signal is asynchronously mapped into an STS-1 SPE important to define and understand all of the following. • The STS-1 frame structure • The STS-1 SPE (Synchronous Payload Envelope) At this point, this DS3 signal has now been 58 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER • Telcordia GR-253-CORE's recommendation on mapping DS3 data into an STS-1 SPE An STS-1 frame is a data-structure that consists of 810 bytes (or 6480 bits). A given STS-1 frame can be viewed as being a 9 row by 90 byte column array (making up the 810 bytes). The frame-repetition rate (for an STS-1 frame) is 8000 frames/second ...
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... TOH (within each STS-1 frame) consists of 3 byte columns x 9 rows = 27 bytes. The byte format of the TOH is presented below in Figure 41. STS RAME TRUCTURE WITH THE 90 Bytes 87 Bytes Envelope Capacity 60 XRT75L06D TOH E AND THE NVELOPE 9 Row ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 41 IGURE HE YTE ORMAT OF THE 3 Byte Columns Rows D10 D10 general, the role/purpose of the TOH bytes is to fulfill the following functions. • ...
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... STS-1 SPE is available for "user" data. The Byte Structure of the STS-1 SPE is presented below in Figure 43. TOH STS-1 F WITHIN AN RAME 87 Byte Columns Envelope Capacity Envelope Capacity Bytes Bytes D11 D12 D11 D12 The TOH Bytes 62 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 43 IGURE LLUSTRATION OF THE 1 Byte Rows general, the role/purpose of the POH bytes is to fulfill the following functions. • To support error detection within the STS-1 SPE • ...
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... Overhead Communication Bits 64 XRT75L06D DS3 DATA INTO 25I 25I 25I 25I 25I 25I 25I ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER Figure 45 presents an alternative illustration of Telcordia GR-253-CORE's recommendation on how to asynchronously map DS3 data into an STS-1 SPE. In this case, the STS-1 SPE bit-format is expressed purely in the form of "bit-types" and "numbers of bits within each of these types of bits". If one studies this figure closely he/she will notice that this is the same " ...
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... STS-1 SPE. Now since each and every STS-1 SPE contains exactly 5592 DS3 data bits; then the bit rate of this DS3 signal will be exactly 44.736Mbps (such as it was when it was mapped into SONET, at the "Source" PTE). DS3 ATA TREAM BEING APPED INTO AN STS-1_Data_Out PTE PTE 51.84MHz + 0ppm 66 XRT75L06D STS-1 SPE, PTE VIA A ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER As a consequence, no "Mapping/De-Mapping" Jitter or Wander is induced in the "Ideal Case". 7.2.2.2 The 44.736Mbps + 1ppm Case The "above example" was a very ideal case. In reality, there are going to be frequency offsets in both the DS3 and STS-1 signals. For instance Bellcore GR-499-CORE mandates that a DS3 signal have a bit rate of 44.736Mbps ± ...
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... Whenever these "positive-stuffing" events occur then (for these particular STS-1 SPEs) the SPE will carry only 5591 DS3 data bits (e.g., in this case, only 2 Stuff Opportunity bits will be carrying DS3 data-bits, and the remaining 7 Stuff Opportunity bits are "stuff" bits). Figure 48 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during this condition. 68 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 48 IGURE N LLUSTRATION OF THE DS3 MAPPING A SIGNAL THAT HAS A BIT RATE OF Source Source PTE PTE 44.736Mbps - 1ppm What does this mean at the Destination PTE? In this case, this DS3 signal (which has now been mapped into an STS-1 data-stream) will be transported across the SONET network. As this STS-1 signal arrives at the " ...
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... H1 and H2 bytes, and indicates which bit-fields are used to reflect the location of the J1 byte. STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAME Byte (1 SPE can straddle across two STS-1 frames 70 XRT75L06D STS-1 FRAMES byte of next SPE) Figure 50 presents an ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 50 IGURE HE IT FORMAT OF THE J1 REFLECTING THE LOCATION OF THE H1 Byte MSB Figure 51 relates the contents within these 10 bits (within the H1 and H2 bytes) to the location of the J1 byte (e.g., the very first byte of the STS-1 SPE) within the Envelope Capacity. ...
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... Now, since the STS-1 signal (which is of frequency f1) is being routed to the network element (which is operating at frequency f2), the typical design approach for handling "clock-domain" differences is to route this STS-1 signal through a "Slip Buffer" as illustrated below. 72 XRT75L06D Typically a ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 52 IGURE N LLUSTRATION OF AN Clock Domain operating At frequency f1 STS-1 Data_IN STS-1 Clock_f1 In the "Slip Buffer, the "input" STS-1 data (labeled "STS-1 Data_IN") is latched into the FIFO, upon a given edge of the corresponding "STS-1 Clock_f1" input clock signal. The STS-1 Data (labeled "STS-1 Data_OUT") is clocked out of the Slip Buffer upon a given edge of the " ...
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... H1 and H2 bytes) that are referred to as "D" bits 16- IT ORMAT WITHIN THE BIT WORD H2 Byte Bit Pointer Expression 74 XRT75L06D ( H1 H2 CONSISTING OF THE AND LSB ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER Figure 54 presents an illustration of the bit format within the 16-bit word (consisting of the H1 and H2 bytes) with the "D" bits designated IGURE N LLUSTRATION OF THE ) "D" BYTES WITH THE BITS DESIGNATED ...
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... Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be A LIU SONET D PPLICATIONS FOR THE IN A De-Mapped (Gapped) DS3 Data and Clock TPDATA_n input pin DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC TCLK_n input 76 XRT75L06D - YNC PPLICATION LIU LIU ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought Mapper IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals (towards the DS3 facility), then it will typically the following manner. ...
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... EQUIREMENTS 1.3UI-pp Includes effects of Jitter from Clock-Gapping, De-Map- ping and Pointer Adjustments. 1.3UI-pp Includes effects of Jitter from Clock-Gapping, De-Map- ping and Pointer Adjustments OINTER DJUSTMENT CENARIO Pointer Adjustment Events >30s Cool Down Measurement Period 78 XRT75L06D T GR-253-CORE, DS3 ELCORDIA FOR C OMMENTS ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 57 IGURE LLUSTRATION OF URST OF Pointer Adjustment Burst Train Initialization Cool Down Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Burst of Pointer Adjustment" scenario, must NOT exceed 1.3UI-pp. ...
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... Figure 60 presents an illustration of the "87-3 Add Pattern" Pointer Adjustment Scenario per Telcordia GR-253- CORE. 87 ONTINUOUS OINTER DJUSTMENT Repeating 87-3 Pattern (see below) Pointer Adjustment Events Measurement Period 87-3 Pattern NOTE: T ranges from 34ms to 10s (Req) T ranges from 7.5ms to 34ms (Obj) 80 XRT75L06D P ATTERN No Pointer Adjustments ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 60. I 87-3 A IGURE LLUSTRATION OF THE 43 Pointer Adjustments T Telcordia GR-253-CORE defines an "87-3 Add" Pointer Adjustment, as the "87-3 Continuous" Pointer Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 60. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the " ...
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... The spacing between individual pointer adjustments (within this scenario) can range from 7.5ms to 10s. 7.5.9 Continuous Add Figure 63 presents an illustration of the "Continuous Add Pattern" Pointer Adjustment Scenario per Telcordia GR-253-CORE ERIODIC OINTER DJUSTMENT Repeating Continuous Pattern (see below) Pointer Adjustment Events Measurement Period 82 XRT75L06D S CENARIO T ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 63 IGURE LLUSTRATION OF ONTINUOUS Continuous Pointer Adjustments T Telcordia GR-253-CORE defines an "Continuous Add" Pointer Adjustment, as the "Continuous" Pointer Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 63. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the " ...
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... EST ESULTS LIU NTRINSIC ITTER EST ESULTS 0.13UI-pp 0.201UI-pp 0.582UI-pp 0.526UI-pp 0.790UI-pp 0.926UI-pp 0.885UI-pp 0.497UI-pp 0.598UI-pp 0.589UI-pp 84 XRT75L06D " SONET/DS3 A FOR PPLICATIONS T GR-253-CORE C I ELCORDIA ATEGORY NTRINSIC ITTER EQUIREMENTS 0.4UI-pp 0.43UI-pp (e.g. 0.13UI-pp + 0.3UI-pp) 1.3UI-pp 1.2UI-pp 1.0UI-pp 1.3UI-pp 1.3UI-pp 1 ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 7.7.2 Wander Measurement Test Results Wander Measurement test results will be provided in the next revision of the LIU Data Sheet. 7.8 Designing with the LIU In this section, we will discuss the following topics. • How to design with and configure the LIU to permit a system to meet the above-mentioned Intrinsic Jitter and Wander requirements. • ...
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... The user can accomplish this by setting Bit 0 (SR/DR*), within the each of the "Channel Control" Registers illustrated below. CHANNEL 1 ADDRESS LOCATION = 0X0E CHANNEL 2 ADDRESS LOCATION = 0X16 RLB_n LLB_n R/W R XRT75L06D E3_n STS-1/DS3_n SR/DR_n R/W R/W R ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 CHANNEL 1 ADDRESS LOCATION = 0X0E CHANNEL 2 ADDRESS LOCATION = 0X16 Unused PRBS Enable Ch_n R/O R/O R • If the LIU has been configured to operate in the Hardware Mode Then the user should tie pin 65 (SR/DR*) to " ...
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... Recovery Ch_n Time DisableCh_n R/W R CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17 SONET APS JA RESET Recovery Ch_n Time DisableCh_n R/W R XRT75L06D JA1 Ch_n Path JA0 Ch_n Ch_n R/W R/W R ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER Our simulation results indicate that Jitter Attenuator PLL (within the LIU LIU IC) will have no problem handling and processing the "Data-Signal" and "Clock-Signal" from a Mapper IC/ASIC if no pre-processing has been performed on these signals. In order words, our simulation results indicate that the Jitter Attenuator PLL (within the LIU IC) will have no problem handling the " ...
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... MAJOR PATTERN B, is exactly the same "MINOR PATTERN P2" as was presented in Figure 39. MINOR PATTERN P3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains no gaps. An illustration of MINOR PATTERN P3 is presented below in Figure 69. Missing Clock Pulse MAJOR PATTERN A YNTHESIZE Repeats 36 Times MINOR PATTERN P2 90 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER F 69. I MINOR PATTERN P3 IGURE LLUSTRATION OF 1 HOW MAJOR PATTERN B IS SYNTHESIZED MAJOR PATTERN B is created (by the Mapper IC) by: • Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times. • Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted repeatedly 36 times. • ...
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... WHICH IS OUTPUT VIA THE PATTERN A PATTERN B LIU SONET D -S BEING USED YNCHRONIZER De-Mapped (Gapped) DS3 Data and Clock TPDATA_n input pin DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC LIU LIU TCLK_n input 92 XRT75L06D "OC-N DS3" APPER " A PPLICATION ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER that are responsible for acquiring and maintaining DS1 or DS3 frame synchronization (with these DS1 or DS3 data-streams that have been de-mapped from SONET) must have re-acquired DS1 or DS3 frame synchronization within 50ms" after APS has been initiated." ...
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... R/W R CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17 SONET APS JA RESET Recovery Ch_n Time Disable Ch_n R/W R XRT75L06D R/W R/W R JA1 Ch_n Path JA0 Ch_n Ch_n ...
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... AXIMUM ATINGS MIN MAX -0.5 6.0 -0.5 5.5 100 -65 150 - 2000 23 LECTRICAL HARACTERISTICS ARAMETER = XRT75L06D UNITS COMMENTS V Note 1 V Note 1 mA Note 1 0 Note linear airflow 0 ft./min C 0 linear air flow 0ft/min C/W (See Note 3 below) level EIA/JEDEC JESD22-A112-A V ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER APPENDIX A T ABLE P ARAMETER Turns Ratio Primary Inductance Isolation Voltage Leakage Inductance P N ART UMBER PE-68629 PE-65966 PE-65967 T 3001 TG01-0406NS TTI 7601-SM TransPower TRANSFORMER VENDOR INFORMATION Pulse Corporate Office 12220 World Trade Drive ...
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... Halo Electronics Corporate Office P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6165 Email: info@haloelectronics.com Website: http://www.haloelectronics.com Transpower Technologies, Inc. Corporate Office Park Center West Building 9805 Double R Blvd, Suite # 100 Reno, NV 89511 (800)500-5930 or (775)852-0140 Email: info@trans-power.com Website: http://www.trans-power.com 97 XRT75L06D ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER P N ART UMBER XRT75L06DIB PACKAGE DIMENSIONS - 217 LEAD BGA PACKAGE ORDERING INFORMATION P ACKAGE 217 Lead BGA ( mm) BOTTOM VIEW (A1 corner feature is mfger option) β Note: The control dimension is in millimeter. ...
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... XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REVISIONS R D EVISION ATE P1.0.0 Original P1.0.2 Renamed the pins DJA and FSS. Included the Clock out and Clock enable func- tion for the Single Frequency Mode. Changed the TxON pin from internal pull down to pull up.Changed the operation of P1 ...