xrt7295at Exar Corporation, xrt7295at Datasheet

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xrt7295at

Manufacturer Part Number
xrt7295at
Description
Xrt7295at -ds3 / Sts-1 Integrated Line Receiver
Manufacturer
Exar Corporation
Datasheet

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Part Number:
xrt7295atIW-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
FEATURES
D Fully Integrated Receive Interface for DS3 and
D Integrated Equalization (Optional) and Timing
D Loss-of-Signal and Loss-of-Lock Alarms
D Variable Input Sensitivity Control
D 5V Power Supply
D Pin Compatible with XRT7295AE and XRT7295AC
D Companion Device to T7296 Transmitter
GENERAL DESCRIPTION
The XRT7295AT DS3/SONET STS-1 integrated line
receiver is a fully integrated receive interface that
terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1
(51.84Mbps) signal transmitted over coaxial cable. (See
Figure 13).
The device also provides the functions of receive
equalization (optional), automatic-gain control (AGC),
clock-recovery and data retiming, loss-of-signal and
loss-of-frequency-lock detection.
interface is dual-rail, with received positive and negative
1s appearing as unipolar digital signals on separate
output leads. The on-chip equalizer is designed for cable
distances of 0 to 450ft. from the cross-connect frame to
the device.
sensitivity control, providing three different sensitivity
ORDERING INFORMATION
STS-1 Rate Signals
Recovery
Rev. 1.20
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
The receive input has a variable input
XRT7295ATIW
Part No.
The digital system
20 Lead 300 Mil JEDEC SOJ
Package
APPLICATIONS
D Interface to DS-3 Networks
D Digital Cross-Connect Systems
D CSU/DSU Equipment
D PCM Test Equipment
D Fiber Optic Terminals
settings, to adapt longer cables. High input sensitivity
allows for significant amounts of flat loss within the
system. Figure 1 shows the block diagram of the device.
The XRT7295AT device is manufactured using linear
CMOS technology. The XRT7295AT is available in a
20-pin plastic SOJ package for surface mounting.
Two versions of the chip are available, one is for either
DS3 or STS-1 operation (the XRT7295AT, this data
sheet), and the other is for E3 operation (the XRT7295AE,
refer to the XRT7295AE data sheet). Both versions are
pin compatible.
For either DS3 or STS-1, an input reference clock at
44.736MHz or 51.84MHz provides the frequency
reference for the device.
Temperature Range
Integrated Line Receiver
-40°C to + 85°C
Operating
DS3/Sonet STS-1
December 2000-2

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xrt7295at Summary of contents

Page 1

... CMOS technology. The XRT7295AT is available in a 20-pin plastic SOJ package for surface mounting. Two versions of the chip are available, one is for either DS3 or STS-1 operation (the XRT7295AT, this data The digital system sheet), and the other is for E3 operation (the XRT7295AE, refer to the XRT7295AE data sheet). Both versions are pin compatible ...

Page 2

BLOCK DIAGRAM REQB 18 Gain & 2 Attenuator Equalizer R IN Detector 19 AGC LOSTHR Analog Equalizer LOS Tuning Ckt. Rev.1.20 LPF1 LPF2 V Phase Slicers Detector Peak Frequency Phase Aquisition Circuit ICT TMC1 TMC2 ...

Page 3

... LOSTHR TMC1 REQB 3 18 LPF1 ICT 4 17 LPF2 RPDATA 5 16 TMC2 RNDATA 6 15 RLOS RCLK 7 14 RLOL EXCLK 8 13 GNDD GNDC Lead SOJ (Jedec, 0.300”) 3 XRT7295AT DD / This pin DD DD ...

Page 4

ELECTRICAL CHARACTERISTICS Test Conditions -40°C to +85° Typical Values are for V = 5.0 V, 25°C, and Random Data. Maximum Values are for V DD Symbol Parameter Electrical Characteristics I Power Supply Current DD DS3 STS--1 ...

Page 5

... In Case 2 of Figure 3, external line build-out (LBO) and equalizer networks precede the XRT7295AT device. In this mode, the signal at R on-chip filters should be bypassed by setting REQB=1. In applications where the XRT7295AT device is used to monitor DS3 transmitter outputs directly, the receive equalizer should be bypassed. Maximum input amplitude under all conditions is 850mV pk ...

Page 6

... CASE CASE 2: 0-450 ft Figure 3. Receiver Configurations Rev.1.20 0 REQB 0.01mF LPF1 LPF2 XRT7295AT Existing Off-chip Networks 0.01mF Fixed 225 ft. R Equalizer LBO 75 Closed For 225-450 ft. Of Cable 6 0.1mF 1 REQB LPF1 0.1mF IN LPF2 XRT7295AT ...

Page 7

... Table 2 and Figure 4)and the G.703 pulse template (see Table 3 and Figure 5). Table 2 and Table 3 give the associated boundary equations for the templates. The the signal XRT7295AT correctly decodes any transmitted signal that meets one of these templates at the cross-connect. Table 1. DSX-3 Interconnection Specification Equation 0 -0.68 ± ...

Page 8

Time Slots - Normalized To Peak Location Figure 4. DSX-3 Isolated Pulse Template for ACCUNET T45 Standards Lower Curve Time T± -0.36 0.5 (1+sin {p/2} [1+T/0.18]) -0.36 ± T±+0.28 0.11e 0.28 ± T ...

Page 9

... The maximum cable distance between the point where the transmitted signal exits the distribution frame jack and the XRT7295AT device is 450 ft. (see Figure 2.) The coaxial cable (Type 728A) used for specifying this pin is 2.8pF distance limitation has the loss and phase characteristics IN shown in Figure 7 and Figure 8 ...

Page 10

... Second, noise sources within the XRT7295AT device and noise sources that are coupled into the device through the power supplies and 12 10 ...

Page 11

... XRT7295AT is shown in Figure 10. FALSE-LOCK IMMUNITY False-lock is defined as the condition where a PLL recovered clock obtains stable phase-lock at a frequency not equal to the incoming data rate. The XRT7295AT device uses a combination architecture to prevent false-lock. An on-chip frequency comparator continuously compares the EXCLK reference to the PLL clock ...

Page 12

... RLOL pulse width is 32 clock cycles. PHASE HITS In response to a phase hit in the input data, the XRT7295AT returns to error free operation in less than 2ms. During the requisition time, RLOS may temporarily be indicated. LOSS-OF-SIGNAL DETECTION Figure 1 shows that analog and digital methods of loss-of-signal (LOS) detection are combined to create the RLOS alarm output ...

Page 13

... This feature /2 threshold level. allows in-circuit testing to be done on neighboring devices DD without concern for XRT7295AT device buffer damage. An internal pull-up device (nominally 50kW) is provided on this pin therefore, users can leave this pin unconnected for normal operation. Test equipment can pull ICT low during in-circuit testing without damaging the device ...

Page 14

... Any noise coupled into the XRT7295AT input directly degrades the signal-to-noise ratio of the input signal and may degrade sensitivity. PLL Filter Capacitor The PLL filter capacitor between pins LPF1 and LPF2 A is bypassed by DD must be placed as close to the chip as possible ...

Page 15

... Cross-Connects,” October 1979. D Compliance with CCITT Recommendations G.703 and G.824, 1988. D Compliance with TR-TSY-000499, “Transport Sys- tems Generic Requirements (TSGR): Common Re- quirements,” December 1988. D Compliance with TA-TSY-000253, “Synchronous Optical Network (SONET) Transport System Gener- ic Criteria,” February 1990. 15 XRT7295AT ...

Page 16

... OUTPUTS RECEIVER MONITOR SW DIP-4 RLOS RLOL XRT7295AT INPUT LOSTHR SIGNAL 8 REQB RLOL ICT RLOS RCLK RNDATA R IN RPDATA 16 0.01mF R2 75 EXTERNAL TMC1 CLOCK B2 TMC2 13 EXCLK 4 R6 GNDA LPF1 75 GNDC C3 0.1mF GNDD 5 LPF2 BT1 FERRITE BEAD C4 0.1mF ...

Page 17

... MIL JEDEC SOJ) Rev. 1. INCHES MILLIMETERS MIN MAX MIN 0.145 0.200 3.60 0.025 --- 0.64 0.120 0.140 3.05 0.014 0.020 0.36 0.008 0.013 0.20 0.496 0.512 12.60 0.292 0.300 7.42 0.262 0.272 6.65 0.050 BSC 1.27 BSC 0.335 0.347 8.51 0.030 0.040 0.76 17 XRT7295AT MAX 5.08 --- 3.56 0.51 0.30 13.00 7.62 6.91 8.81 1.02 ...

Page 18

... While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ...

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