wm8988 Wolfson Microelectronics plc, wm8988 Datasheet - Page 38

• Manufacturer Part Number: wm8988
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

WM8988
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MASTER MODE LRC ENABLE
In Master mode the lrclk (LRC) is enabled by default only when the DAC is enabled. If ADC only
operation in Master mode is required register bit LRCM must be set in oder to generate an lrclk. For
DAC only operation LRCM may be set to ‘0’.
Table 33 LRC Enable
BIT CLOCK MODE
The default master mode bit clock generator produces a bit clock frequency based on the sample
rate and input MCLK frequency as shown in Table 36. When enabled by setting the appropriate
BCM[1:0] bits, the bit clock mode (BCM) function overrides the default master mode bit clock
generator to produce the bit clock frequency shown in the table below:
Table 34 Master Mode BCLK Frequency Control
The BCM mode bit clock generator produces 16 or 24 bit clock cycles per sample. The number of bit
clock cycles per sample in this mode is determined by the word length bits (WL[1:0]) in the Digital
Audio Interface Format register (R7). When these bits are set to 00, there will be 16 bit clock cycles
per sample. When these bits are set to 01, 10 or 11, there will be 24 bit clock cycles per sample.
Please refer to Figure 18.
In order to use BCM either the ADC must be enabled or, if the ADC is disabled, the LRCM bit must
be set and the DAC enabled.
When the BCM function is enabled, the following restrictions apply:
1. The bit clock invert (BCLKINV) function is not available.
2. DSP late digital audio interface mode is not available and must not be enabled.
Figure 18 Bit Clock Mode
Note: The shaded bit clock cycles are present only when 24-bit mode is selected. Please refer to the
“Bit Clock Mode” description for details.
R24(18h)
Additional
Control (2)
R8 (08h)
Clocking and
Sample Rate
Control
REGISTER
REGISTER
ADDRESS
ADDRESS
BIT
BIT
8:7
2
BCM[1:0]
LABEL
LABEL
LRCM
DEFAULT
DEFAULT
00
0
Selects disable mode for LRC
0 = LRC disabled when DAC (Left and Right)
1 = LRC disabled only when ADC (Left and
BCLK Frequency
00 = BCM function disabled
01 = MCLK/4
10 = MCLK/8
11 = MCLK/16
disabled.
Right) and DAC (Left and Right) are
disabled.
DESCRIPTION
DESCRIPTION
PD, Rev 4.0, October 2008
Production Data
38