wm8988 Wolfson Microelectronics plc, wm8988 Datasheet - Page 44

• Manufacturer Part Number: wm8988
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

WM8988
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STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8988, the master clock may be
stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In
Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.
However, since setting DIGENB has no effect on the power consumption of other system
components external to the WM8988, it is preferable to disable the master clock at its source
wherever possible.
Table 40 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set
to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may
prevent DACs and ADCs from re-starting correctly.
SAVING POWER BY REDUCING BIAS CURRENTS
The design of the DAC allows user trade-off between power consumption and performance, using
the DACMIXBIAS bit. The default setting (DACMIXBIAS=0) delivers the best audio performance.
Setting DACMIXBIAS=1 reduces AVDD current consumption, at the cost of marginally reduced
performance (see “Electrical Characteristics” for details).
Table 41 DAC Biasing
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 128x oversampling mode.
Under the control of ADCOSR and DACOSR the oversampling rate may be halved. This will result in
a slight decrease in noise performance but will also reduce the power consumption of the device. In
USB mode ADCOSR must be set to 0, i.e. 128x oversampling.
Table 42 ADC and DAC Oversampling Rate Selection
ADCOSR set to ‘1’, 64x oversample mode, is not supported in USB mode (USB=1).
R25 (19h)
Additional Control
(1)
R67 (43h)
R24 (18h)
Additional Control
(2)
REGISTER
ADDRESS
REGISTER
REGISTER
ADDRESS
ADDRESS
3
BIT
0
1
0
DACMIX
BIAS
BIT
BIT
LABEL
DIGENB
ADCOSR
DACOSR
LABEL
LABEL
0
DEFAULT
0
0
0
DEFAULT
DEFAULT
DAC biasing
0 = high bias current (results in higher
1 = low bias current (results in lower
performance and power consumption)
performance and power consumption)
Master clock disable
0: master clock enabled
1: master clock disabled
DESCRIPTION
ADC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
DAC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
PD, Rev 4.0, October 2008
DESCRIPTION
DESCRIPTION
Production Data
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