wm8988 Wolfson Microelectronics plc, wm8988 Datasheet - Page 39

• Manufacturer Part Number: wm8988
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
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CLOCKING AND SAMPLE RATES
The WM8988 supports a wide range of master clock frequencies on the MCLK pin, and can generate
many commonly used audio sample rates directly from the master clock. The ADC and DAC must
always run at the same sample rate.
There are two clocking modes:
•
•
Table 35 Clocking and Sample Rate Control
The clocking of the WM8988 is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination
of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their
accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change
proportionately.
Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their
target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%
(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%
change in pitch.
The SR[4:0] bits must be set to configure the appropriate ADC and DAC sample rates in both master
and slave mode.
R8 (08h)
Clocking and
Sample Rate
Control
REGISTER
ADDRESS
‘Normal’ mode supports master clocks of 128f
(Note: f
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio codec.
s
refers to the ADC or DAC sample rate, whichever is faster)
6
5:1
0
BIT
CLKDIV2
SR [4:0]
USB
LABEL
0
00000
0
s
DEFAULT
, 192f
s
, 256f
s
, 384f
Master Clock Divide by 2
1 = MCLK is divided by 2
0 = MCLK is not divided
Sample Rate Control
Clocking Mode Select
1 = USB Mode
0 = ‘Normal’ Mode
s
, and their multiples
PD, Rev 4.0, October 2008
DESCRIPTION
WM8988
39