wm9701acftv Wolfson Microelectronics plc, wm9701acftv Datasheet - Page 13

• Manufacturer Part Number: wm9701acftv
• Description: Power Ac97 Multimedia Audio Codec
• Manufacturer: Wolfson Microelectronics plc

Production Data
AC-LINK AUDIO INPUT FRAME (SDATA_IN)
WOLFSON MICROELECTRONICS LTD.
If a sample stream of resolution less than 20-bits is transferred, the AC’97 controller must stuff all
trailing non-valid bit positions within this time slot with 0s.
SLOT 5: OPTIONAL MODEM LINE CODEC
Audio output frame slot 5 contains the MSB justified modem DAC input data. This optional AC’97
feature is not supported in WM9701A, and if data is written to this location it is ignored. This may be
determined by the AC’97 controller interrogating the WM9701A Vendor ID registers.
SLOTS 6-12: RESERVED
Audio output frame slots 6-12 are reserved for future use and are always stuffed with 0s by the
AC’97 controller.
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC’97 controller. As is the case for audio output frame, each AC-link audio input frame
consists of 12, 20-bit time slots.
Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol
infrastructure.
Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether WM9701A is in
the “Codec Ready” state or not. If the “Codec Ready” bit is a 0, this indicates that WM9701A is not
ready for normal operation. This condition is normal following the desertion of power on reset for
example, while WM9701A’s voltage references settle. When the AC-link “Codec Ready” indicator bit
is a 1 it indicates that the AC-link and WM9701A control and status registers are in a fully
operational state. The AC’97 controller must further probe the power down Control/Status Register to
determine exactly which subsections, if any, are ready.
Prior to any attempts at putting WM9701A into operation the AC’97 controller should poll the first bit
in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that WM9701A has gone “Codec
Ready”.
Once WM9701A is sampled “Codec Ready” then the next 12 bit positions sampled by the AC’97
controller indicate which of the corresponding 12 time slots are assigned to input data streams, and
that they contain valid data. Figure 10 illustrates the time slot based AC-link protocol.
There are several subsections within WM9701A that can independently go busy/ready. It is the
responsibility of the WM9701A controller to probe more deeply into the WM9701A register file to
determine which WM9701A subsections are actually ready.
Figure 11 Start of an Audio Input Frame
A new audio input frame begins with a low to high transition of SYNC as shown in Figure 11. SYNC
is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,
WM9701A samples the assertion of SYNC. This falling edge marks the time when both sides of AC-
link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC’97
controller transitions SDATA_IN into the first bit position of slot 0 (valid frame bit). Each new bit
position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the
AC’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data
transitions and subsequent sample points for both incoming and outgoing data streams are time
aligned.
SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0’s by WM9701A. SDATA_IN is sampled on the
falling edges of BIT_CLK .
SDATA_IN
BIT_CLK
SYNC
End of previous Audio Frame
WM9701A samples SYNC assertion
AC’97 Controller samples first
SDATA_IN bit of frame here
Codec
Ready
Slot (1)
Slot (2)
PD Rev 3.2 January 2001
WM9701A
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