wm8351 Wolfson Microelectronics plc, wm8351 Datasheet - Page 211

• Manufacturer Part Number: wm8351
• Description: Wolfson Audioplus? Stereo Codec With Power Management
• Manufacturer: Wolfson Microelectronics plc

Production Data
w
R44 (2Ch) FLL Control 3
R45 (2Dh) FLL Control 4
R60 (3Ch) DAC Side
R39 (27h) Comparator Interrupt
R40 (28h) Clock Control 1
R41 (29h) Clock Control 2
R42 (2Ah) FLL Control 1
R43 (2Bh) FLL Control 2
R48 (30h) DAC Control
R50 (32h) DAC Digital Volume L
R51 (33h) DAC Digital Volume R
R53 (35h) DAC LR Rate
R54 (36h) DAC Clock Control
R58 (3Ah) DAC Mute
R59 (3Bh) DAC Mute Volume
R64 (40h) ADC Control
R66 (42h) ADC Digital Volume L
R67 (43h) ADC Digital Volume R
R68 (44h) ADC Divider
R70 (46h) ADC LR Rate
R72 (48h) Input Control
R73 (49h) IN3 Input Control
R74 (4Ah) Mic Bias Control
REG
Status Mask
NAME
IM_EXT_US
DACR_ENA
ADCR_ENA
B_FB_EINT
TOCLK_EN
LRC_ADC_
DACL_ENA
ADC_HPF_
ADCL_ENA
MICB_ENA MICB_SEL
IN3R_ENA IN3R_SHO
FLL_ENA FLL_OSC_E
SEL
ENA
15
(s)
A
0
0
0
0
0
0
0
0
0
0
DAC_MUTE
DAC_MUTE
TOCLK_RA
IM_EXT_W
ALL_FB_EI
MODE
NT (s)
14
TE
NA
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL_RATIO[4:0]
IM_EXT_BA
DAC_MUTE
TT_FB_EIN
DAC_MON
ADC_TO_DACL[1:0]
RATE
T (s)
13
0
0
O
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
DAC_SB_FI
AIF_LRCLK
RATE
12
LT
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_CODEC
_JCK_DET_
DACLRC_E
ADCLRC_E
MCLK_SEL
L_EINT (s)
ADC_TO_DACR[1:0]
11
NA
NA
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
_JCK_DET_
IM_CODEC
R_EINT (s)
IN2R_ENA IN1RN_ENA IN1RP_ENA
ADCL_DAC_SVOL[3:0]
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL_OUTDIV[2:0]
IM_CODEC
_MICSCD_
EINT (s)
ADC_HPF_CUT[1:0]
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_MICD_EIN
IM_CODEC
MCLK_DIV
DAC_VU
DAC_VU
ADC_VU
ADC_VU
T (s)
8
0
0
0
0
0
0
0
0
0
FLL_K[15:0]
MIC_DET_E
FLL_REF_F
IN3L_ENA IN3L_SHOR
REQ
7
NA
0
0
0
0
0
0
0
0
0
IM_WKUP_
OFF_STAT
E_EINT (s)
ADCR_DAC_SVOL[3:0]
FLL_RSP_RATE[3:0]
6
BCLK_DIV[3:0]
T
0
0
0
0
0
0
0
0
0
0
DACLRC_RATE[10:0]
ADCLRC_RATE[10:0]
HIB_STATE
IM_WKUP_
FLL_FRAC
_EINT (s)
5
0
0
0
0
0
0
0
0
0
DEEMP[1:0]
FLL_N[9:0]
CONV_FAU
LT_EINT (s)
DACCLK_P
IM_WKUP_
4
OL
DACL_VOL[7:0]
DACR_VOL[7:0]
ADCL_VOL[7:0]
ADCR_VOL[7:0]
0
0
0
0
0
0
0
0
MCDTHR[2:0]
DAC_SDMC
IM_WKUP_
WDOG_RS
ADCCLK_P
T_EINT (s)
LK_RATE
3
OL
0
0
0
0
0
0
0
0
0
0
0
IM_WKUP_
GP_PWR_
IN2L_ENA IN1LN_ENA IN1LP_ENA
ON_EINT
2
(s)
0
0
0
0
0
0
0
0
DAC_CLKDIV[2:0]
ADC_CLKDIV[2:0]
OPCLK_DIV[2:0]
FLL_RATE[2:0]
DACL_DATI
ADCL_DATI
IM_WKUP_
ONKEY_EI
NT (s)
FLL_CLK_SRC[1:0]
NV
NV
MCDSCTHR[1:0]
1
0
0
0
0
0
PD, June 2009, Rev 4.1
DACR_DATI
ADCR_DATI
IM_WKUP_
GP_WAKE
MCLK_DIR
UP_EINT
0
(s)
NV
NV
0
0
0
0
WM8351
DEFAULT
3A00h
C226h
00C0h
00C0h
00C0h
00C0h
0000h
0040h
0000h
7086h
0000h
0000h
0040h
0000h
4000h
0000h
0000h
8000h
0000h
0040h
0303h
0000h
0000h
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