wm8351 Wolfson Microelectronics plc, wm8351 Datasheet - Page 48
wm8351
Manufacturer Part Number
wm8351
Description
Wolfson Audioplus? Stereo Codec With Power Management
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8351.pdf
(328 pages)
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When the GPIO5 pin is configured as CODEC_OPCLK, a clock derived from SYSCLK may be output
on this pin to provide clocking for other parts of the system. The frequency of this signal is set by
OPCLK_DIV.
Alternate GPIO pins can be used to provide ADCLRCLK and ADCBCLK as described in Section 20.
An inverted L/R clock signal ADCLRCLKB can also be generated. When this feature is used, the
LRCLK and BCLK pins support the DAC only, and the alternate GPIO pins support the ADC only.
Limited capability can be provided to support mixed sample rates by this method. (The selection of
USB mode and the supported values of the various SYSCLK dividers impose restrictions on what
combinations of clocking and sample rates may be configured.)
A slow clock derived from SYSCLK may be used to provide de-bouncing of the headphone detect
function, and to set the timeout period for volume updates when zero-cross functions are used. This
clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
The overall CODEC clocking scheme is illustrated in Figure 35.
Figure 35 Audio CODEC Clocking
PD, June 2009, Rev 4.1
Production Data
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