wm8351 Wolfson Microelectronics plc, wm8351 Datasheet - Page 267

• Manufacturer Part Number: wm8351
• Description: Wolfson Audioplus? Stereo Codec With Power Management
• Manufacturer: Wolfson Microelectronics plc

Production Data
Register 82h GPIO Pull down Control
w
REGISTER
REGISTER
ADDRESS
ADDRESS
R131 (83h)
Interrupt
GPIO
Mode
BIT
BIT
12
11
10
9
4
3
2
1
0
GP12_INTMODE
GP11_INTMODE
GP10_INTMODE
GP9_INTMODE
LABEL
GP4_PD
GP3_PD
GP2_PD
GP1_PD
GP0_PD
LABEL
DEFAULT
DEFAULT
0
0
1
0
0
0
0
0
0
0
0
0
Reset by state machine. Default held in metal mask.
GPIO4 pull-down
0 = Normal
1 = Pull-down enabled
(Only valid when GPIO4 is set to input. Do not select
pull-up and pull-down at the same time.)
Reset by state machine. Default held in metal mask.
GPIO3 pull-down
0 = Normal
1 = Pull-down enabled
(Only valid when GPIO3 is set to input. Do not select
pull-up and pull-down at the same time.)
Reset by state machine. Default held in metal mask.
GPIO2 pull-down
0 = Normal
1 = Pull-down enabled
(Only valid when GPIO2 is set to input. Do not select
pull-up and pull-down at the same time.)
Reset by state machine. Default held in metal mask.
GPIO1 pull-down
0 = Normal
1 = Pull-down enabled
(Only valid when GPIO1 is set to input. Do not select
pull-up and pull-down at the same time.)
Reset by state machine. Default held in metal mask.
GPIO0 pull-down
0 = Normal
1 = Pull-down enabled
(Only valid when GPIO0 is set to input. Do not select
pull-up and pull-down at the same time.)
Reset by state machine. Default held in metal mask.
GPIO12 Pin Mode
0 = GPIO interrupt is rising edge triggered, and is
taken after the effect of the GP12_CFG register bit.
1 = GPIO interrupt is both rising and falling edge
triggered.
Reset by state machine.
GPIO11 Pin Mode
0 = GPIO interrupt is rising edge triggered, and is
taken after the effect of the GP11_CFG register bit.
1 = GPIO interrupt is both rising and falling edge
triggered.
Reset by state machine.
GPIO10 Pin Mode
0 = GPIO interrupt is rising edge triggered, and is
taken after the effect of the GP10_CFG register bit.
1 = GPIO interrupt is both rising and falling edge
triggered.
Reset by state machine.
GPIO9 Pin Mode
DESCRIPTION
DESCRIPTION
PD, June 2009, Rev 4.1
REFER TO
REFER TO
WM8351
267