tsl2561cs Pacer Components, tsl2561cs Datasheet - Page 12

• Manufacturer Part Number: tsl2561cs
• Description: Light-to-digital Converter
• Manufacturer: Pacer Components

TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059L − JANUARY 2008
NOTE: The I
NOTE: The I
Register Set
12
Copyright E 2008, TAOS Inc.
1
S
1
S
The TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register
accessed through the serial interface. These registers provide for a variety of control functions and can be read
to determine results of the ADC conversions. The register set is summarized in Table 2.
The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section
on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status
register for following read/write operations.
Slave Address
Slave Address
Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
2
2
C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
7
7
ADDRESS
Figure 15. SMBus Block Read or I
Ch
Dh
−−
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Eh
Fh
Wr
Wr
1
1
A
A
1
1
Figure 14. SMBus Block Write or I
THRESHHIGHHIGH
THRESHLOWHIGH
THRESHHIGHLOW
THRESHLOWLOW
RESISTER NAME
Command Code
Command Code
INTERRUPT
DATA0HIGH
DATA1HIGH
DATA0LOW
DATA1LOW
COMMAND
CONTROL
TIMING
CRC
−−
−−
ID
−−
Data Byte 1
8
8
r
8
Table 2. Register Address
www.taosinc.com
Specifies register address
Control of basic functions
Integration time/gain control
Low byte of low interrupt threshold
High byte of low interrupt threshold
Low byte of high interrupt threshold
High byte of high interrupt threshold
Interrupt control
Reserved
Factory test — not a user register
Reserved
Part number/ Rev ID
Reserved
Low byte of ADC channel 0
High byte of ADC channel 0
Low byte of ADC channel 1
High byte of ADC channel 1
A
A
1
1
A
1
Sr
1
2
C Read (Combined Format) Protocols
Byte Count = N
Slave Address
Data Byte 2
Data Byte 2
8
7
2
REGISTER FUNCTION
8
C Write Protocols
8
Rd
A
1
1
A
A
1
1
r
1
A
...
...
Data Byte 1
Byte Count = N
8
The LUMENOLOGY r Company
8
Data Byte N
Data Byte N
8
8
A
1
1
A
...
...
A
A
1
1
1
1
1
P
P