apa075 Actel Corporation, apa075 Datasheet - Page 171

• Manufacturer Part Number: apa075
• Description: Proasicplus Flash Family Fpgas
• Manufacturer: Actel Corporation

Previous version
Advanced v0.6
(continued)
Advanced v0.5
Advanced v0.4
Advanced v0.3
Advanced v0.3
(continued)
Advanced v0.1
The description for the V
The
The
The
The
The
The
The
The
Figure 1-12
The
The
The
The
The
The
The
The
The
WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent
with the signal names found in the Macro Library Guide.
Figure 1-21
The
The table in the
The
The
The ’Nominal Supply Voltages’ section has been updated.
The
The
updated.
The
The
Figure 1-14
Figure 1-13
Tables 5, 6, and 7 from Advanced v0.3 were removed.
The
The
All pinout tables have been updated, and several packages are new:
208-Pin PQFP – APA150, APA300, APA450, APA600
456-Pin PBGA – APA150, APA300, APA450, APA600
144-Pin FBGA – APA150, APA300, APA450
256-Pin FBGA – APA150, APA300, APA450, APA600
676-Pin FBGA – APA600
Figure 1-23
Changes in current version (v5.5)
"Synchronous Write and Read to the Same Location" section
"Asynchronous Write and Synchronous Read to the Same Location" section
"Asynchronous FIFO Read" section
"Pin Description" section
"Recommended Design Practice for VPN/VPP" section
"100-Pin TQFP" section
"484-Pin FBGA" section
"Plastic Device Resources" section
"Tristate Buffer Delays" section
"Output Buffer Delays" section
"Input Buffer Delays" section
"Global Input Buffer Delays" section
"456-Pin PBGA" section
"676-Pin FBGA" section
"ProASICPLUS Product Profile" section
"Plastic Device Resources" section
"ProASICPLUS I/O Power Supply Voltages"
"Design Environment" section
"Calculating Typical Power Dissipation" section
"Programming, Storage, and Operating Limits" section
"DC Electrical Specifications (VDDP = 2.5 V ±0.2V)" section
"DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V)" section
"Recommended Operating Conditions" section
"ProASICPLUS Clock Management System" section
"Memory Block SRAM Interface Signals" section
"Memory Block FIFO Interface Signals" section
and
and
was updated.
is new.
has been updated.
"Package Thermal Characteristics" section
Figure 1-13
Figure 1-22
PN
pin has changed.
is new.
have been updated.
have been updated.
is new.
has been updated.
has been updated.
has been updated.
has been updated.
and
has been updated.
has been updated.
has been updated.
has been updated.
Figure 1-26
was updated.
has been updated.
has been changed.
v5.5
sectionhas been updated.
was updated.
have been updated.
is new.
was updated.
was updated.
was updated.
is new.
has been updated.
is new.
was updated.
was updated.
ProASIC
was updated.
PLUS
was
Flash Family FPGAs
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