apa075 Actel Corporation, apa075 Datasheet - Page 75

• Manufacturer Part Number: apa075
• Description: Proasicplus Flash Family Fpgas
• Manufacturer: Actel Corporation

Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 1-45 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Table 1-63 • T
Symbol t
CCYC
CMH
CML
ECBA
FCBA
ECBH, FCBH,
THCBH
OCA
OCH
RDCH
RDCS
RPCA
RPCH
HCBA
Notes:
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
2. All –F speed grade devices are 20% slower than the standard numbers.
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
Clock high phase
Clock low phase
FULL ↓ access from RCLKS ↓
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RCLKS ↓
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
Old RPE valid from RCLKS ↑
Cycle time
New EMPTY access from RCLKS ↓
New DO access from RCLKS ↑
New RPE access from RCLKS ↑
EQTH or GETH access from RCLKS ↓
EQTH, GETH
Description
DD
RDATA
EMPTY
RCLK
DD
FULL
= 2.3 V to 2.7 V for Commercial/industrial
RDB
RPE
= 2.3 V to 2.7 V for Military/MIL-STD-883
t RDCS
t RDCH
Old Data Out
t RPCH
t OCH
t OCA
t RPCA
Cycle Start
t CMH
Min.
3.0
3.0
7.5
3.0
3.0
7.5
0.5
1.0
9.5
4.5
v5.5
t CCYC
1
1
New Valid Data Out (Empty Inhibits Read)
Max.
t THCBH
1.0
3.0
3.0
t HCBA
t CML
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t ECBH , t FCBH
t ECBA , t FCBA
Empty/full/thresh are invalid from the end
of hold until the new access is complete
ProASIC
PLUS
Notes
Flash Family FPGAs
1-69