rt9232a Richtek Technology Corporation, rt9232a Datasheet - Page 12

• Manufacturer Part Number: rt9232a
• Description: Programmable Frequency Synchronous Buck Controller
• Manufacturer: Richtek Technology Corporation

RT9232A
The compensation network consists of the error amplifier
EA and the impedance networks Z
the compensation network is to provide a closed loop
transfer function with the highest DC gain, the highest
0dB crossing frequency (F
Typically, F
adequate. The higher F
is. A phase margin in the range of 45°C~ 60°C is desirable.
The equations below relate the compensation network
poles, zeros and gain to the components (R1, R2, R3,
C1, C2, and C3) in Figure 4.
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12
F
F
F
F
Z1
Z2
P1
P2
=
=
=
=
ΔV
2
2
2
2
π
π
OSC
π
π
x
x
x
x
R2
R2
OSC
C
R3
(R1
1
1
in range 1/5~1/10 of switching frequency is
Comparator
x
x
1
x
+
1
V
C1
PWM
C1
C1
C3
COMP
R3)
E/A
C1
-
+
EA
+
x
Z
FB
EA
C2
x
C2
C2
-
+
REF
C3
-
+
C
R2
Figure 4
is, the faster dynamic response
REF
C
FB
Z
) and adequate phase margin.
FB
Driver
Driver
C3
Z
R1
IN
IN
Z
R3
IN
V
and Z
IN
PHASE
V
OUT
C
L
OUT
ESR
FB
(12)
(13)
(14)
(15)
. The goal of
V
OUT
Feedback Loop Design Procedure
Use these guidelines for locating the poles and zeros of
the compensation network:
1. Pick Gain (R2/R1) for desired 0dB crossing frequency
(F
2. Place 1
(~75% F
3. Place 2
4. Place 1
5. Place 2
6. Check gain against error amplifier’s open-loop gain.
7. Pick R
8. Estimate phase margin and repeat if necessary.
Layout Consideration
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability. First, place the PWM power stage components.
Mount all the power components and connections in the
top layer with wide copper areas. The MOSFETs of Buck,
inductor, and output capacitor should be as close to each
other as possible. This can reduce the radiation of EMI
due to the high frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered. Place the input capacitor directly to the drain
C
100
-20
-40
-60
).
80
60
40
20
0
10
LC
FB
20LOG
(R1/R2)
ND
ND
ST
ST
).
for desired output voltage.
pole F
zero F
pole F
zero F
Modulator
100
Gain
Z1
Z2
Z2
Z1
1K
F
at the ESR zero F
at half the switching frequency.
at modulator double pole F
Z1
below modulator double pole F
F
LC
Figure 5
F
Frequency (Hz)
Z2
10K
F
20LOG
(V
P1
F
DS9232A-02 March 2007
IN
ESR
/ΔV
100K
F
P2
OSC
)
Z_ESR
Open Loop Error
AMP Gain
Closed Loop Gain
1M
Compensation
Gain
10M
LC
.
LC