rt9232a Richtek Technology Corporation, rt9232a Datasheet - Page 9
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rt9232a
Manufacturer Part Number
rt9232a
Description
Programmable Frequency Synchronous Buck Controller
Manufacturer
Richtek Technology Corporation
Datasheet
1.RT9232A.pdf
(14 pages)
Application Information
The RT9232A is a single-phase synchronous buck PWM
DC-DC converter controller designed to drive two N-Channel
MOSFETs. It provides a highly accurate, programmable
output voltage precisely regulated to low voltage
requirement with an internal 0.8V ±1% reference.
Initialization
The RT9232A automatically initiates its softstart cycle
only after VCC and V
are ready. There is no special power-on sequence should
be took care especially while implement the chip in. The
internal Power-On Reset (POR) logic continually monitors
the voltage level of input power and enabling pin; in which
the IC supply power is monitored via VCC pin and input
power V
with driving capability of 200uA causes a fixed voltage
drop across the resistor connecting V
The RT9232A internal logic will deem the input voltage
ready once the voltage of SENSE pin is high than 1.5V.
The preferred V
appropriate resistor R
Once all voltages of VCC, SENSE, and EN pins ramp
higher than the internal specific thresholds. The internal
POR logic will initialize the softstart operation then.
Moreover, the POR inhibits driver operation while pulling
the EN pin low. Transitioning EN pin high after input supply
voltages ready to initialize soft-start operation.
Soft-Start
The behavior of RT9232A Soft-Start can be simply
described as shown as Figure.1 below; and the Soft-Start
can be sliced to several time-frames with specific operation
respectively.
T0~T1
The RT9232A initiates the softstart cycle as shown in
Figure 1 when POR function is OK. An internal 10uA current
source charges an external capacitor on SS pin (Css) to
5V. The softstart function produces an SSE signal that is
equal to (SS-1.2V)/2. Error Amplifier (EA) and PWM
comparator are triple-input devices. The non-inverting input
DS9232A-02 March 2007
R
SENSE
<
IN
V
is via SENSE pin. An internal current source
IN_READY
200
IN
ready level could be set by selecting an
μ
A
−
IN
SENSE
1.5V
power and chip enabling signals
as:
Ω
IN
to SENSE pin.
whichever is smaller dominates the behavior of the devices.
During T0~T1, since SS is smaller than the sawtooth valley,
the PWM comparator outputs low no matter what the
COMP voltage is.
T1~T2
During T1~T2, EA keeps COMP voltage low that makes
the PWM output low.
T2~T3
SSE ramps up and dominates the behavior of EA during
T2~T3. EA regulates COMP appropriately so that FB
ramps up along the SSE curve. The output voltage ramps
up accordingly. Thus upper MOSFET turns on at a limited
duty and output current overshoot can be reduced.
It is noted that lower MOSFET keeps off before the upper
MOSFET starts switching. This method provides smooth
start up when there is residual voltage on output capacitors.
The output voltage delay time and ramp up time are
calculated as Equation (1) and (2) respectively.
T2
T3
0.8V
1V
5V
−
−
T0
T0
T2
=
=
Figure 1. Timing diagram of softstart
1.2V x
1.6V x
0.8V
T1T2
FB
10uA
10uA
C
C
SSE
SS
SS
(s)
(s)
EA
T3
COMP
(1)
(2)
SS
RT9232A
PWM
www.richtek.com
COMP
SS
SSE
FB
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