ox16pci954 ETC-unknow, ox16pci954 Datasheet - Page 52

• Manufacturer Part Number: ox16pci954
• Description: Integrated Quad Uart Interface
• Manufacturer: ETC-unknow

8.3
The configuration registers for the local bus controller are
described in sections 6.4.3 & 6.4.4. The values of these
registers after reset allow the host system to identify the
function and configure its base address registers.
Alternatively many of the default values can be re-
programmed during device initialisation through use of the
optional serial EEPROM (see section 10).
The I/O space block can be varied in size from 4 bytes to
256 bytes (32 bytes is the default) by setting LT2[22:20]
accordingly. Varying the block size means that I/O space
can be allocated efficiently by the system, whatever the
application.
The I/O block can then be divided into one, two or four
chip-select regions, depending on the setting in LT2[26:23].
To divide the area into four chip-select region, the user
should select the second uppermost non-zero address bit
as the Lower-Address-CS-decode. To divide into two
regions, the user should select the uppermost address bit.
If an address bit beyond the selected range is selected, the
entire I/O space is allocated to CS0#. For example, if 32
bytes of I/O space are reserved, the active address lines
are A[4:0]. To divide this into four regions, the Lower
Address CS parameter should be set to A3, by
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
Configuration & Programming
programming the value ‘0001’ into LT2[26:23]. To select
two regions, choose A4, and to maintain one region, select
any value greater than A4.
In 8-bit mode, the memory space block is always 4K bytes,
and always divided into four chip-select regions of 1K byte
each.
In 32-bit mode, again the I/O space can be varied in size
from 4 bytes to 256 bytes. It is also possible to increase the
memory space block size from 4K bytes to 16K bytes. Also
in 32-bit mode, the Lower-Address-CS-Decode parameter
afftects division of the I/O space AND memory space into
chip-select regions.
A soft reset facility is provided so software can
independently reset the peripherals on the local bus. The
local bus reset signals, LBRST and LBRST#, are always
active during a PCI bus reset and also when the
configuration register bit LT2[29] is set to 1.
The clock enable bit, when set, enables a copy of the PCI
bus clock output on the local bus pin LBCLK. A buffered
UART clock can also be asserted on the UART_Clk_Out
pin; this means that a single oscillator can be used to drive
serial ports on the local bus as well as the internal UARTs.
OX16PCI954
Page 52