ox16pci954 ETC-unknow, ox16pci954 Datasheet - Page 54

• Manufacturer Part Number: ox16pci954
• Description: Integrated Quad Uart Interface
• Manufacturer: ETC-unknow

9.3
The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block).
Note 1 : These registers are only available in EPP mode.
Note 2 : Prefix ‘n’ denotes that a signal is inverted at the connector. Suffix ‘#’ denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX). The reset value of DSR is ‘XXXXX111’. DCR and
ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
9.3.1
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 will drive data onto the parallel port data lines.
In all other modes the drivers may be tri-stated by setting
the direction bit in the DCR. Reads from this register return
the value on the data lines.
Data Sheet Revision 1.3
(Other modes)
OXFORD SEMICONDUCTOR LTD.
(EPP mode)
Register
EPPD1
EPPD2
EPPD3
EPPD4
EPPA
Name
DCR
PDR
DSR
ECR
-
-
-
Register Description
Parallel port data register ‘PDR’
1
1
1
1
1
Address
Offset
000h
001h
001h
002h
003h
004h
005h
006h
007h
400h
401h
402h
403h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
-
-
-
nBUSY
nBUSY
Bit 7
0
SPP (Compatibility Mode) Registers
Table 30: Parallel port register set
Mode[2:0]
ACK#
ACK#
Bit 6
0
Bit 5
DIR
PE
PE
Parallel Port Data Register
9.3.2
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
from the peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 9.1.3)
DSR[0]:
EPP mode: Timeout
logic 0
logic 1
Other modes: Unused
This bit is permanently set to 1.
DSR[1]: Unused
This bit is permanently set to 1.
EPP Address Register
EPP Data 1 Register
EPP Data 2 Register
EPP Data 3 Register
EPP Data 4 Register
Bit 4
Reserved – Must write ‘00001’
INT_EN
SLCT
SLCT
Reserved
Reserved
Reserved
Device status register ‘DSR’
Timeout has not occurred.
Timeout has occurred (Reading this bit clears it).
Bit 3
nSLIN#
ERR#
ERR#
Bit 2
INIT#
INT#
INT#
Bit 1
nAFD#
1
1
OX16PCI954
Bit 0
Timeout
Page 54
nSTB#
1