f25l008a Elite Semiconductor Memory Technology Inc., f25l008a Datasheet - Page 9

• Manufacturer Part Number: f25l008a
• Description: 3v Only Serial Flash Memory
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L008A. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low transition of CE . Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE must be driven
TABLE 5: DEVICE OPERATION INSTRUCTIONS
1.
2.
3.
4.
5.
6.
7.
8.
Elite Semiconductor Memory Technology Inc.
10
RY/BY#
Read
High-Speed-Read
Sector-Erase
Block-Erase (64K Byte)
Chip-Erase
Byte-Program
Auto-Address-Increment-wor
d programming (AAI)
Read-Status-Register
(RDSR)
Enable-Write-Status-Registe
r
(EWSR)
Write-Status-Register
(WRSR)
Write-Enable (WREN)
Write-Disable (WRDI)
Read-Electronic-Signature
(RES)
Jedec-Read-ID (JEDEC-ID)
Read-ID (RDID)
Enable SO to output RY/BY#
Status during AAI (EBSY)
Disable
Status during AAI (DBSY)
Operation: S
X = Dummy Input Cycles (V
One bus cycle is eight clock periods.
Sector addresses: use AMS-A12, remaining addresses can be V
Prior to any Byte-Program, Sector-Erase , Block-Erase ,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
Operation
Cycle Type/
8
8
SO
6
4,5
5
IN
(4K Byte)
= Serial In, S
to
1,2
11
output
100
OUT
IL
33
50
Freq
Max
or V
MHz
MHz
MHz
= Serial Out
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
90H
90H
ADH
0BH
D8H
C7H
ABH
03H
20H
60H
02H
05H
50H
01H
06H
04H
9FH
70H
80H
S
IN
(A0=0)
(A0=1)
1
S
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z A
Hi-Z
Hi-Z
OUT
Data
23
23
23
23
23
23
23
S
X
X
X
-A
-A
-A
-A
-
-A
-A
-
-A
-
-
-
-
IN
16
16
16
16
16
16
16
2
D
S
8CH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
13H
IL
OUT
OUT
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
-
-
-
-
-
or V
IH
A
A
A
A
A
A
A
15
15
15
15
15
15
15
S
X
-
-
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
-A
-A
8
8
8
8
8
8
8
Bus Cycle
3
Note
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
20H
OUT
-
-
-
-
-
-
-
7
Publication Date: Jul. 2008
Revision:
A
A
A
A
A
A
A
S
7
7
7
7
7
7
7
-.
X
-A
-A
-A
-A
-
-A
-A
-
-
-
-
-A
-
-
IN
0
0
0
0
0
0
0
4
Note
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z D
Hi-Z D
14H
Hi-Z
OUT
-
-
-
-
-
-
-
1.6
7
F25L008A
S
X
X
X
IN
-
-
-
-
-
-
-
-
-
-
-
IN
IN
0
5
Note
S
D
8CH
Hi-Z
Hi-Z
13H
OUT
OUT
X
-
-
-
-
-
-
-
-
-
-
9/32
7
D
S
X
X
IN
IN
1
6
D
S
8CH
Hi-Z
13H
OUT
OUT